TLC5954 Datasheet, PDF (4/45 Pages) Texas Instruments – TLC5954 48-Channel, Constant-Current LED Driver with Global Brightness Control, LED Open-Short Detection, and Power-Save Mode

TLC5954
SBVS241 – APRIL 2014
www.ti.com
NAME
GND
OUTR0 to
OUTR15
OUTG0 to
OUTG15
OUTB0 to
OUTB15
PIN
NO.
1, 56
2, 5, 8, 11, 14, 17, 20,
23, 30, 33, 36, 39, 44,
47, 50, 53
3, 6, 9, 12, 15, 18, 21,
24, 31, 34, 37, 40, 45,
48, 51, 54
4, 7, 10, 13, 16, 19, 22,
25, 32, 35, 38, 41, 46,
49, 52, 55
SIN
26
LAT
27
SCLK
28
BLANK
29
SOUT
VCC
42
43
Thermal pad
Pin Functions
I/O DESCRIPTION
— Ground. All GND pins are connected internally.
Red LED constant-current outputs (OUTRn).
O
Multiple outputs can be tied together to increase the constant-current capability. Different voltages can be
applied to each output. These outputs are turned on or off by the BLANK signal and the data in the output on
or off control data latch.
Green LED constant-current outputs (OUTGn).
O
Multiple outputs can be tied together to increase the constant-current capability. Different voltages can be
applied to each output. These outputs are turned on or off by the BLANK signal and the data in the output on
or off control data latch.
Blue LED constant-current outputs (OUTBn).
O
Multiple outputs can be tied together to increase the constant-current capability. Different voltages can be
applied to each output. These outputs are turned on or off by the BLANK signal and the data in the output on
or off control data latch.
Serial data input of the 49-bit common shift register, Schmitt buffer input.
I
When SIN is high, the LSB is set to 1 for only one SCLK input rising edge. If two SCLK rising edges are input
while SIN is high, then the 49-bit shift register LSB and LSB+1 are set to 1. When SIN is low, the LSB is set to
0 at the SCLK input rising edge.
Edge-triggered latch, Schmitt buffer input.
The LAT rising edge latches data from the common shift register either into the output on or off data latch or
I
the maximum current control (MC), brightness control (BC), or function control (FC) data latch. When the
common shift register data are latched into the on or off data latch, data in the common shift register are
simultaneously replaced with SID, which is selected by SIDLD. Refer to the Output On or Off Data Latch and
Status Information Data (SID) sections for more details.
Serial data shift clock, Schmitt buffer input.
I
Data present on SIN are shifted to the 49-bit common shift register LSB with the SCLK rising edge. Data in the
shift register are shifted towards the MSB at each SCLK rising edge. The common shift register MSB appears
on SOUT.
Blank all outputs, Schmitt buffer input.
I When BLANK is high, all constant-current outputs (OUTXn) are forced off. When BLANK is low, all OUTXn are
controlled by the on or off control data in the data latch.
O
Serial data output of the 49-bit common shift register.
SOUT is connected to the MSB of the register. Data are clocked out at the SCLK rising edge.
— Power-supply voltage
— Ground. The thermal pad must be connected to GND on the printed circuit board (PCB).
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)⁽¹⁾
VCC
V_IN
V_OUT
T_J (max)
Supply voltage⁽²⁾
Input voltage range
SIN, SCLK, LAT, BLANK
Output voltage range
SOUT
OUTR0 to OUTR15, OUTG0 to OUTG15,
OUTB0 to OUTB15
Operating junction temperature
MIN
MAX
UNIT
–0.3
4.0
V
–0.3
V_CC + 0.3
V
–0.3
V_CC + 0.3
V
–0.3
11
V
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to device ground pin.
4
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