TLC5954 Datasheet, PDF (27/45 Pages) Texas Instruments – TLC5954 48-Channel, Constant-Current LED Driver with Global Brightness Control, LED Open-Short Detection, and Power-Save Mode

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TLC5954
SBVS241 – APRIL 2014
8.5 Register Maps
8.5.1 Register and Data Latch Configuration
The device has one common shift register and four control data latches. These data latches are the output on or
off data latch, the maximum current control (MC) data latch, the global brightness control (BC) data latch, and the
function control (FC) data latch.
The common shift register is 49 bits long, the output on or off data latch is 48 bits long, and another 48-bit data
latch is comprised of the 40-bit MC, BC, and FC data latches with an 8-bit write command decoder. If the
common shift register MSB is 0, the least significant 48 bits of data from the 49-bit common shift register are
latched into the output on or off data latch. If the MSB (bit 48) from the 49-bit common shift register is 1 and MSB
1 through MSB 9 (bits [47:40]) are 96h (10010110b) for the write command data, the middle 37 bits (bits [39:3])
in the common shift register are latched into the BC and FC data latch. MC data are updated when the same
data are written to the MC bits twice with the write command data (96h) and the MSB (bit 48) set to 1. Figure 34
shows the configuration of the common shift register and the four data latches.
Common Shift Register (49 Bits)
SOUT
MSB
Data
Select bit
Common
Data bit
47
Common
Data bit
46
Common
Data bit
45
Common Common
Data bit Data bit
44
43
48
47
46
45
44
43
LSB
Common Common Common Common Common Common
Data bit Data bit Data bit Data bit Data bit Data bit
5
4
3
2
1
0
---
5
4
3
2
1
0
SIN
SCK
48 Bits
48 Bits
Output On or Off Data Latch (48 Bits)
MSB
OUTB15 OUTG15 OUTR15 OUTB14 OUTG14
On
On
On
On
On
47
46
45
44
43
48 Bits
LSB
OUTB1 OUTG1 OUTR1 OUTB0 OUTG0 OUTR0
On
On
On
On
On
On
---
5
4
3
2
1
0
This latch pulse is
generated when LAT
rising edge is input
with “0” MSB data of
common shift register
(Data select bit).
Higher 8 Bits
Middle 37 Bits
Lower 3 Bits
3 Bits
Pre-MC Data Latch
(3 Bits)
Xlat
The
previous
MC data
RESET from UVLO
Xreset
3 Bits
3 Bits
3 Bits
LatMC
3 Bits
MSB
LSB
8-Bit Write
Command Decoder,
96h (10010110b) Latch
47 --- 40
MSB
FC for SIDLD, LODVLT,
LSDVLT, PSMODE and
7-Bit Reserved Bit
39
---
24
BC for
OUTB0-15
23 --- 17
BC for
OUTG0-15
16 --- 10
LSB
BC for
OUTR0-15
9 --- 3
BC, FC Data Latch (37 Bits)
MSB
LSB
MC for
All
OUTXn
2 ^--- 0
MC Data Latch (3 Bits)
This latch pulse is generated when the LAT rising edge is input
with the MSB data of the common shift register = 1 (data select bit).
Figure 34. Common Shift Register and Data Latch Configuration
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