DRV104_16 Datasheet, PDF (4/26 Pages) Texas Instruments – 1.2A PWM High-Side Driver for Solenoids, Coils, Valves, Heaters, and Lamps

PIN CONFIGURATION
Top View
HTSSOP
Top View
SO
Duty Cycle Adj 1
Delay Adj 2
Osc Freq Adj 3
Master 4
Boot 5
OUT1 6
OUT2 7
DRV104
PowerPAD
14 Input
13 Status OK Flag
12 SYNC
11 GND
10 +V_S
9 V_PS1
8 V_PS2
Duty Cycle Adj 1
Delay Adj 3
Osc Freq Adj 5
GND 7
14 Input
DRV103
PowerPAD
DRV103 for Reference
12 Status OK Flag
10 +V_S
8 OUT
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
1 Duty Cycle Adjust Internally, this pin connects to the input of a comparator and a (2.75 x I_REF) current source from V_S. The voltage at this node linearly
sets the duty cycle. The duty cycle can be programmed with a resistor, analog voltage, or the voltage output of a D/A converter. The
active voltage range is from 1.3V to 3.9V to facilitate the use of single-supply control electronics. At 3.56V, the output duty cycle is
near 90%. At 1.5V, the output duty cycle is near 10%. Internally, this pin is forced to 1.24V. No connection is required when the device
is in slave mode.
2
Delay Adjust This pin sets the duration of the initial 100% duty cycle before the output goes into PWM mode. Leaving this pin floating results in
a delay of approximately 18µs, which is internally limited by parasitic capacitance. Minimum delay may be reduced to less than 3µs
by tying the pin to 5V. This pin connects internally to a 15µA current source from V_S and to a 2.6V threshold comparator. When the
pin voltage is below 2.6V, the output device is 100% On. The PWM oscillator is not synchronized to the Input (pin 1), so the duration
of the first pulse may be any portion of the programmed duty cycle. No connection is required when the device is in slave mode.
3
Oscillator
PWM frequency is adjustable. A resistor to ground sets the current I_REF and the internal PWM oscillator frequency. A range of 500Hz
Frequency Adjust to 100kHz can be achieved with practical resistor values. Although oscillator frequency operation below 500Hz is possible, resistors
higher than 10MΩ will be required. The pin then becomes a very high-impedance node and is, therefore, sensitive to noise pickup
and PCB leakage currents. Resistor connection to this pin in slave mode sets the frequency at which current limit reset occurs.
4
Master
With no connection, this pin is driven to 5V by an internal 15µA current source. In this mode the device is the master and the SYNC
pin becomes a 0V to 4.2V output, which is High when the power device is on. When the Master/Input is 0V, the SYNC pin is an
input. In slave mode, the output follows the SYNC pin; the output is High when SYNC is High.
5
BOOT
The bootstrap capacitor between this pin and the output, supplies the charge to provide the V_GS necessary to turn on the power
device. C_BOOT should be larger than 100pF. Use of a smaller C_BOOT may slow the output rise time, device is specified and tested
with 470pF.
6, 7
OUT1, OUT2 The output is the source of a power DMOS transistor with its drain connected to V_PS. Its low on-resistance (0.45Ω typ) assures
low power dissipation in the DRV104. Gate drive to the power device is controlled to provide a slew-rate limited rise-and-fall time.
This reduces the radiated RFI/EMI noise. A flyback diode is needed with inductive loads to conduct the load current during the off
cycle. The external diode should be selected for low forward voltage and low storage time. The internal diode should not be used
as a flyback diode. If devices are connected in parallel, the outputs must be connected through individual diodes. Devices are
current-limit protected for shorts to ground, but not to supply.
8, 9
V_PS1, V_PS2
These are the load power-supply pins to the drain of the power device. The load supply voltage may exceed the voltage at pin 10
by 5V, but must not exceed 37V.
10
+V_S
This is the power-supply connection for all but the drain of the power device. The operating range is 8V to 32V.
11
GND
This pin must be connected to the system ground for the DRV104 to function. It does not carry the load current when the power
DMOS device is switched on.
12
SYNC
The SYNC pin is a 0V to 4.2V copy of the output when the Master/Slave pin is High. As an output, it can supply 100µA with 1kΩ
output resistance. At 2mA, it current limits to either 4.2V or 0V. When the Master pin is Low, it is an input and the threshold is 2V.
SYNC output follows power output in master mode, and is not affected by thermal or current-limit shutdown. Power output follows
SYNC input in slave mode.
13 Status OK Flag Normally High (active Low), a Flag Low signals either an over-temperature or over-current fault. A thermal fault (thermal shutdown)
occurs when the die surface reaches approximately 160°C and latches until the die cools to 140°C. This output requires a pull-
up resistor and it can typically sink 2mA, sufficient to drive a low-current LED. Sink current is internally limited at 10mA, typical.
14
Input
The input is compatible with standard TTL levels. The device becomes enabled when the input voltage is driven above the typical
switching threshold, 1.8V; below this level, the device is disabled. Input current is typically 1µA when driven High and 1µA when driven
Low. The input should not be directly connected to the power supply (V_S) or damage will occur.
4
DRV104
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