DAC8581_16 Datasheet, PDF (4/20 Pages) Texas Instruments – 16-BIT, HIGH-SPEED, LOW-NOISE, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER

DAC8581
Not Recommended For New Designs
SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
All specifications at T_A = T_MIN to T_MAX, +AV_DD = +5 V, –AV_DD = –5 V, DV_DD = +5 V (unless otherwise noted).
DAC8581
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
POWER SUPPLY
+AV_DD
–AV_DD
DV_DD
I_DVDD
I_DD
I_SS
TEMPERATURE RANGE
I_REF and IDV_DD included
4.0
5
–4.0
–5
1.8
10
17
–23
6.0
–6.0
AV_DD
20
24
–32
Specified performance
–40
+85
UNIT
V
V
V
μA
mA
mA
°C
PIN CONFIGURATION
V_REF
V_OUT
AV_SS
AV_DD
AGND
DGND
DGND
DGND
PW PACKAGE
TSSOP-16
(TOP VIEW)
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
DV_DD
DGND
CLR
DV_DD
DGND
CS
SCLK
SDIN
TERMINAL
NAME
NO.
V_REF
1
VOUT
2
AV_SS
3
AV_DD
4
AGND
5
DGND
6, 7, 8, 15
SDIN
9
SCLK
10
CS
11
DGND
12
DV_DD
13
CLR
14
DV_DD
16
TERMINAL FUNCTIONS
Reference input voltage.
DAC output voltage. Output swing is ±V_REF
Negative analog supply voltage, tie to –5 V
Positive analog supply voltage, tie to +5 V
The ground reference point of all analog circuitry of the device. Tie to 0 V.
Tie to DGND to ensure correct operation.
Digital input, serial data. Ignored when CS is high.
Digital input, serial bit clock. Ignored when CS is high.
Digital input. Chip Select (CS) signal. Active low. When CS is high, SCLK and SDI are ignored. When CS is low,
data can be transferred into the device.
Ground reference for digital circuitry. Tie to 0 V.
Positive digital supply, 1.8 V–5.5 V compatible
Digital input for forcing the output to midscale. Active low. When pin CLR is low during 16^th SCLK following the
falling edge of CS, the falling edge of 16^th SCLK sets DAC Latch to midcode, and the DAC output to 0 V. When
pin CLR is High, the falling edge of 16th SCLK updates DAC latch with the value of input shift register, and
changes DAC output to corresponding level.
Tie to DV_DD to ensure correct operation.
4
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