DAC8581_16 Datasheet, PDF (10/20 Pages) Texas Instruments – 16-BIT, HIGH-SPEED, LOW-NOISE, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER

DAC8581
Not Recommended For New Designs
SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012
www.ti.com
Glitch area is low at 0.5 nV-s, with peak glitch amplitude under 10 mV, and the glitch duration under 100 ns. Low
glitch is obtained for code-to-code (small signal) changes across the entire transfer function of the device. For
large signals, settling characteristics of the reference and output amplifiers are observed in terms of overshoot
and undershoot.
Combined with ±5-V output range, and extremely good noise performance, the outstanding differential linearity
performance of this device becomes significant. That is, each DAC step can be clearly observed at the DAC
output, without being corrupted by wideband noise.
SERIAL INTERFACE
The DAC8581 serial interface consists of the serial data input pin SDIN, bit clock pin SCLK, and chip-select pin,
CS. The serial interface is designed to support the industry standard SPI interface up to 50 MHz. The serial
inputs are 1.8-V to 5.5-V logic compatible.
CS operates as an active-low, chip-select signal. The falling edge of CS initiates the data transfer. Each rising
edge of SCLK following the falling edge of CS shifts the SDIN data into a 16-bit shift register, MSB-first. At the
16th rising edge of SCLK, the shift register becomes full and the DAC data updates on the falling edge that
follows the 16th rising edge. After the data update, further clocking gets ignored. The sequence restarts at the
next falling edge of CS. If the CS is brought high before the DAC data are updated, the data are ignored. See the
timing diagram (Figure 1) for details.
Pin CLR
Pin CLR is implemented to set the DAC output to 0 V. When the CS pin is low during the 16th SCLK cycle
following the falling edge of CS, the falling edge of the 16th SCLK sets the DAC latch to midcode, and the DAC
output to 0 V. If the CLR pin is high during the 16th clock, the falling edge of the 16th clock updates the DAC
latch with the input data. Therefore, if the CLR pin is brought back to High from Low during serial communication,
the DAC output stays at 0 V until the falling edge of the next 16th clock is received. The CLR pin is active low.
CLR low does not affect the serial data transfer. The serial data input doe not get interrupted or lost while the
output is set at midscale.
SCLK
This digital input pin is the serial bit-clock. Data are clocked into the device at the rising edge of SCLK.
CS
This digital input pin is the chip-select signal. When CS is low, the serial port is enabled and data can be
transferred into the device. When CS is high, all SCLK and SDIN signals are ignored.
SDIN
This digital input is the serial data input. Serial data are shifted on the rising edge of the SCLK when CS is low.
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