DAC8581_16 Datasheet, PDF (3/20 Pages) Texas Instruments – 16-BIT, HIGH-SPEED, LOW-NOISE, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER

Not Recommended For New Designs
DAC8581
www.ti.com
SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012
ELECTRICAL CHARACTERISTICS
All specifications at T_A = T_MIN to T_MAX, +AV_DD = +5 V, –AV_DD = –5 V, DV_DD = +5 V (unless otherwise noted).
DAC8581
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STATIC PERFORMANCE
Resolution
16
Bits
Linearity error
Differential linearity error
V_REF = 4.096 V
±0.03
±0.25
±0.1 %FS
±0.5 LSB
Gain error
1
2
3 %FS
Gain drift
±5
ppm/°C
Bipolar zero error
–5
±25 mV
Bipolar zero drift
±20
μV/°C
Total drift
±10
ppm/°C
OUTPUT CHARACTERISTICS
Voltage output
V_REF up to 5.5 V, when AV_DD = 6 V, AV_SS = –6
V
–V_REF
V_REF
V
Output impedance
1
Ω
Maximum output current
±25
mA
Settling time
Slew rate⁽¹⁾
C_L < 200 pF, R_L = 2 kΩ, to 0.1% FS, 8-V step
To 0.003% FS
0.65
μs
1
35
V/μs
Code change glitch
1 LSB change around major carry
0.5
nV-S
Overshoot
Digital feedthrough⁽²⁾
Full-scale change
50
mV
0.5
nV-S
SNR
Digital sine wave input, f_OUT = 1 kHz,
BW = 10 kHz, 2-MSPS update rate
108
dB
THD
Output voltage noise
Digital sine wave input, f_OUT = 20 kHz,
8-V_PP output, 2-MSPS update rate
0.1 Hz to 10 Hz
At 10-kHz offset frequency
–72
dB
25
μV_PP
25
nV/√Hz
At 100-kHz offset frequency
20
nV/√Hz
Power supply rejection
VDD varies ±10%
0.75
mV/V
REFERENCE
Reference input bandwidth
Reference input voltage range
Reference input impedance
Large signal: 2-V_PP sine wave on 4 V DC
Small signal: 100-mV_PP sine wave on 4 V DC
3
MHz
10
MHz
3
AV_DD
V
5
kΩ
Reference input capacitance
5
pF
DIGITAL INPUTS
V_IH
V_IL
Input current
GND
0.7 x DV_DD
V
0.3 x DV_DD
±1 μA
Input capacitance
10
pF
Power-on delay
From V_DD high to CS low
20
μs
(1) Slew rate is measured from 10% to 90% of transition when the output changes from 0 to full-scale.
(2) Digital feedthrough is defined as the impulse injected into the analog output from the digital input. It is measured when the DAC output
does not change, CS is held high, and while SCLK and SDIN signals are toggled.
Copyright © 2005–2012, Texas Instruments Incorporated
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