BQ2026 Datasheet, PDF (4/22 Pages) Texas Instruments – 1.5K-Bit Serial EPROM With SDQ Interface

bq2026
SLUS938 – DECEMBER 2011
Table 2. EPROM Status Bytes
ADDRESS (HEX)
100h-107h
PAGE
General Purpose OTP Status Memory
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Error Checking
Error checking can be implemented by comparing the 16-bit CRC values transmitted by the bq2026. If the two
CRC values match, the transmission is error-free. Details are found in the CRC Generation section of this data
sheet.
Customizing the bq2026
The 64-bit ID identifies each bq2026. The 48-bit serial number is unique and programmed by Texas Instruments.
The default 8-bit family code is 09h; however, a different value can be reserved on an individual customer basis.
Contact your Texas Instruments sales representative for more information.
Bus Termination
Because the drive output of the bq2026 is an open-drain, N-channel MOSFET, the host must provide a source
current or a 5-kΩ external pullup, as shown in the typical application circuit in Figure 1.
bq2026
SDQI
Communications
Controller
VPU
SDQ
1
CPU
SDQO
VSS
3
VSS
2
HOST
Figure 1. Typical Applications Circuit
Serial Communication
A host reads, programs, or checks the status of the bq2026 through the hierarchical command structure of the
SDQ interface. Figure 2 shows that the host must first issue a ROM command before the EPROM memory or
status can be read or modified.
Initialization
ROM Command Sequence
Memory/Status Command Sequence
Figure 2. General Command Sequence
Initialization
Initialization consists of two pulses, the RESET and the PRESENCE pulses. The host generates the RESET
pulse, while the bq2026 responds with the PRESENCE pulse. The host resets the bq2026 by driving the DATA
bus low for at least 480 μs. For more details, see the RESET section under SDQ Signaling.
4
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