BQ2026 Datasheet, PDF (11/22 Pages) Texas Instruments – 1.5K-Bit Serial EPROM With SDQ Interface

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bq2026
SLUS938 – DECEMBER 2011
WRITE STATUS
The Write Status command is used to program the EPROM Status data field after the bq2026 has been selected
by a ROM command
The flow chart in Figure 9 illustrates that the host issues the Write Status command, 55h, followed by the
address low byte and then the address high byte followed by the byte of data to be programmed.
NOTE
Individual bytes of address and data are transmitted LSB first. a 16-bit CRC of the
command byte, address bytes, and data byte is computed by the bq2026 and read back
by the host to confirm that the correct command word, starting address, and data byte
were received.
If the CRC read by the host is incorrect, a reset pulse must be issued and the entire sequence must be repeated.
If the CRC received by the host is correct, the programming voltage, V_PP is applied to the SDQ pin for period
t_PROG. Prior to programming, the first 7 bytes of the EPROM STATUS data field appear as logical 1s. For each bit
in the data byte provided by the host that is set to a logical 0, the corresponding bit in the selected byte of the
EPROM STATUS data field is programmed to a logical 0 after the programming pulse has been applied at the
byte location.
After the programming pulse is applied and the data line returns to V_PU, the host issues eight read time slots to
verify that the appropriate bits have been programmed. The bq2026 responds with the data from the selected
EPROM STATUS address sent least significant bit first. This response should be checked to verify the
programmed byte. If the programmed byte is incorrect, then the host must reset the device and begin the write
sequence again. If the bq2026 EPROM data byte programming was successful, the bq2026 automatically
increments its address counter to select the next byte in the STATUS MEMORY data field. The least significant
byte of the new two-byte address is also loaded into the 16-bit CRC generator as a starting value. The host
issues the next byte of data using eight write time slots.
As the bq2026 receives this byte of data into the RAM buffer, it also shifts the data into the CRC generator that
has been preloaded with the LSB of the current address and the result is a 16-bit CRC of the new data byte and
the new address. After supplying the data byte, the host reads this 16-bit CRC from the bq2026 with eight read
time slots to confirm that the address incremented properly and the data byte was received correctly. If the CRC
is incorrect, a Reset Pulse must be issued and the Write Status command sequence must be restarted. If the
CRC is correct, the host issues a programming pulse and the selected byte in memory is programmed.
NOTE
The initial write of the WRITE STATUS command, generates a 16-bit CRC value that is
the result of shifting the command byte into the CRC generator, followed by the
two-address bytes, and finally the data byte. Subsequent writes within this WRITE
STATUS command due to the bq2026 automatically incrementing its address counter
generates a 16-bit CRC that is the result of loading (not shifting) the LSB of the new
(incremented) address into the CRC generator and then shifting in the new data byte.
For both of these cases, the decision to continue programming the EPROM Status registers is made entirely by
the host, because the bq2026 is not able to determine if the 16-bit CRC calculated by the host agrees with the
16-bit CRC calculated by the bq2026. If an incorrect CRC is ignored and a program pulse is applied by the host,
incorrect programming could occur within the bq2026. Also note that the bq2026 always increments its internal
address counter after the receipt of the eight read time slots used to confirm the programming of the selected
EPROM byte. The decision to continue is again made entirely by the host, therefore if the EPROM data byte
does not match the supplied data byte but the master continues with the WRITE STATUS command, incorrect
programming could occur within the bq2026. The WRITE STATUS command sequence can be ended at any
point by issuing a reset pulse.
Copyright © 2011, Texas Instruments Incorporated
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