BQ2026 Datasheet, PDF (13/22 Pages) Texas Instruments – 1.5K-Bit Serial EPROM With SDQ Interface

www.ti.com
bq2026
SLUS938 – DECEMBER 2011
READ
The READ bit timing diagram in Figure 12 shows that the host initiates the transmission of the bit by issuing the
t_RSTRB portion of the bit. The bq2026 then responds by either driving the DATA bus low to transmit a READ 0 or
releasing the DATA bus to transmit a READ 1.
VPU _{V IH}
V _IL
Read ”1”
Read ”0”
t _RSTRB
t _ODD
t _ODHO
Figure 12. Read Bit Timing Diagram
t _REC
PROGRAM PULSE
V_PP
V_PU
V_SS
t_PSU
t_PRE
t_EPROG
t_PFE
t_PREC
Figure 13. Program Pulse Timing Diagram
IDLE
If the bus is high, the bus is in the IDLE state. Bus transactions can be suspended by leaving the DATA bus in
IDLE. Bus transactions can resume at any time from the IDLE state.
CRC Generation
The bq2026 has a 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master can compute
a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the bq2026 to
determine if the ROM data has been received error-free by the bus master. The equivalent polynomial function of
this CRC is shown in Figure 14.
Under certain conditions, the bq2026 also generates a 16-bit CRC value using the polynomial function is shown
in Figure 15 and provides this value to the bus master which validates the transfer of command, address, and
data bytes from the bus master to the bq2026. The bq2026 computes a 16-bit CRC for the command, address,
and data bytes received for the WRITE MEMORY and the WRITE STATUS commands, and then outputs this
value to the bus master which confirms proper transfer. Similarly, the bq2026 computes a 16-bit CRC for the
command and address bytes received from the bus master for the READ MEMORY, and READ STATUS
commands to confirm that these bytes have been received correctly.
In each case, where a CRC is used for data transfer validation, the bus master must calculate a CRC value
using the polynomial function in Figure 14 or Figure 15 and compares the calculated value to either the 8-bit
CRC value stored in the 64-bit ROM portion of the bq2026 (for ROM reads) or the 16-bit CRC value computed
within the bq2026. The comparison of CRC values and the decision to continue with an operation are determined
entirely by the bus master. No circuitry on the bq2026 prevents a command sequence from proceeding if the
CRC stored in or calculated by the bq2026 does not match the value generated by the bus master. Proper use of
the CRC can result in a communication channel with a high level of integrity.
SPACER
Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s) :bq2026
Submit Documentation Feedback
13