BQ2026 Datasheet, PDF (12/22 Pages) Texas Instruments – 1.5K-Bit Serial EPROM With SDQ Interface

bq2026
SLUS938 – DECEMBER 2011
Table 3. Command Code Summary
COMMAND
(HEX)
33h
55h
CCh
F0h
AAh
0Fh
55h
DESCRIPTION
Read Serialization ROM and CRC
Match Serialization ROM
Skip Serialization ROM
Read Memory/Field CRC
Read EPROM Status
Write Memory
Write EPROM Status
CATEGORY
ROM Commands Available in Command Level I
Memory Function Commands
Available in Command Level II
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SDQ SIGNALING
All SDQ signaling begins with initializing the device, followed by the host driving the bus low to write a 1 or 0, or
to begin the start frame for a bit read. Figure 10 shows the initialization timing, whereas Figure 11 and Figure 12
show that the host initiates each bit by driving the DATA bus low for the start period, t_WSTRB / t_RSTRB. After the bit
is initiated, either the host continues controlling the bus during a WRITE, or the bq2026 responds during a
READ.
RESET AND PRESENCE PULSE
If the DATA bus is driven low for more than 120 μs, the bq2026 may be reset. Figure 10 shows that if the DATA
bus is driven low for more than 480 μs, the bq2026 resets and indicates that it is ready by responding with a
PRESENCE PULSE.
V_PU
V_IH
V_IL
RESET
(Sent by Host)
t_RST
t_PPD
Presence Pulse
(Sent by bq2026)
t_PP
t_RSTREC
Figure 10. Reset Timing Diagram
WRITE
The WRITE bit timing diagram in Figure 11 shows that the host initiates the transmission by issuing the t_WSTRB
portion of the bit and then either driving the DATA bus low for a WRITE 0, or releasing the DATA bus for a
WRITE 1.
VPU _VIH
V _IL
Write ”1”
Write ”0”
t _WSTRB
t _rec
t _WDSU
t _WDH
Figure 11. Write Bit Timing Diagram
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