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TLC320AD56 Datasheet, PDF (39/42 Pages) Texas Instruments – Sigma-Delta Analog Interface Circuit | |||
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Appendix A
Register Set
Bits D12 through D8 in a secondary serial communication comprise the address of the register that is written
with the data carried in D7 through D0. D13 determines a read or write cycle to the addressed register. When
low, a write cycle is selected.
Table Aâ1 shows the register map.
Table Aâ1. Data and Control Registers
BITS
REGISTER NO.
REGISTER NAME
D15 D14 D13 D12 D11 D10 D9 D8
0
00000000
No operation
1
00000001
Control 1
2
00000010
Control 2
Table Aâ2. Control 1 Register
BITS
D7 D6 D5 D4 D3 D2 D1 D0
DESCRIPTION
1 â â â â â â â Software reset
0 â â â â â â â Software reset not asserted
â 1 â â â â â â Software power down (analog and filters)
â 0 â â â â â â Software power down (not asserted)
â â 1 â â â â â Select AUXP and AUXM
â â 0 â â â â â Select INP and INM
â â â 0 â â â â Select INP and INM for monitor
â â â 1 â â â â Select AUXP and AUXM for monitor
â â â â 1 1 â â Monitor amp gain = â 18 dB (see Note B)
â â â â 1 0 â â Monitor amp gain = â 8 dB (see Note B)
â â â â 0 1 â â Monitor amp gain = 0 dB (see Note B)
â â â â 0 0 â â Monitor amp mute
â â â â â â 1 â Digital loopback asserted
â â â â â â 0 â Digital loopback not asserted
â â â â â â â 1 16-bit mode (hardware secondary requests)
â â â â â â â 0 Not 16-bit mode (software secondary requests)
NOTES: A. Default value: 00000000
B. These gains are for a single-ended input. The gain is 6 dB lower with a differential input.
The software reset is a one-shot operation and this bit is cleared to 0 after reset. It is not necessary to write
a zero to end the master reset operation. Writing 0s to the reserved bits is suggested.
Aâ1
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