TLC320AD56 Datasheet, PDF (26/42 Pages) Texas Instruments – Sigma-Delta Analog Interface Circuit

3.3 Conversion Rate vs Serial Port
The SCLK frequency is set by the frequency of MCLK. There is a 2-stage clock divider that sets the SCLK
frequency as MCLK/4.
3.4 Phone Mode Control
Phone mode control is provided for applications that need hardware control and monitoring of external
events. By allowing the device to drive two FLAG terminals (set through the Control 2 register), the host
(DSP) is capable of system control through the same serial port that connects to the device. Along with this
control is the capability of monitoring the value of the ALT DATA terminal during a secondary communication
cycle. One application for this function is in monitoring RING DETECT or OFFHOOK DETECT from a phone
answering system. The two FLAG terminals allow response to these incoming control signals. Figure 3–6
shows the timing associated with this operating mode.
Primary
Secondary
Primary
Secondary
Primary
FS
DOUT
(Secondary
Read)
ALT DATA
8 SCLKs
Register
Data
ALT DATA
DOUT
(Secondary
Write)
ÏÏÏÏÏÏÏÏÏÏ _{ALT DATA}
ÏÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏÏÏÏ _DIN
ÏÏÏÎÎÏÎÎÏÎÎÎÎÎÎÏÎÎÏÎÎÏÏ ÏÏÏÏ ÏÏÏÏÏÏÏ _FLAG0,
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ^FLAG1
1 SCLK MAX
Set FLAG0 = FLAG1 = 1
Set FLAG0 = FLAG1 = 0
Figure 3–5. Phone Mode Timing
(SecoRndeDaa^{ÏÏIdrNy) ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏDo8ÏÏNBoittsÏÏCareÏÏÏÏÏÏÏÏÏÏÏÏ}
(SecoWndrDiat^{ÏÏÏIreNy) ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏR/WÏÏÏÏÏÏReÏÏÏgisteÏÏÏrAdÏÏÏdreÏÏÏss ÏÏÏÏÏÏ8ÏÏÏBitsÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ}
Data to the
Register
Figure 3–6. Secondary DIN Format
3–6