TLC320AD56 Datasheet, PDF (11/42 Pages) Texas Instruments – Sigma-Delta Analog Interface Circuit

1.5 Terminal Functions
TERMINALS
NAME
NUMBER I/O
PT FN
DESCRIPTION
ALT DATA
25
19
I
Signals on this terminal are routed to DOUT during secondary communication
if phone mode is enabled.
AUXM
38
26
I
Inverting input to auxiliary analog input. AUXM requires an external RC antialias
filter.
AUXP
Noninverting input to auxiliary analog input. Requires an external RC antialias
39 27 I _filter.
AVDD
DIN
33 23 I Analog ADC path supply (5 V only)
10
11
I
Data input. DIN receives the DAC input data and command information from the
DSP and is synchronized to SCLK.
DOUT
Data output. DOUT transmits the ADC output bits and is synchronized to SCLK.
12 12 O _{This terminal is at high-Z when FS is not activated.}
DVDD
DVSS
FC
9 10 I Digital power supply (5 V or 3 V)
26 20 I Digital ground
Function code. FC is sampled and latched on the rising edge of FS for the primary
21 16 I serial communication. Refer to the Serial Communications section for more
details.
FLAG 0
23
17
O
Output flag 0. During phone mode, FLAG 0 contains the value set in Control 2
register.
FLAG 1
24
18
O
Output flag 1. During phone mode, FLAG 1 contains the value set in Control 2
register.
Bandgap filter. FILT is provided for decoupling of the bandgap reference, and
FILT
47
3
O
provides 2.5 V to which the analog inputs or outputs can be referenced. The
optimal capacitor value is 0.1 µF (ceramic). This voltage node should be loaded
only with a high-impedance dc load.
Frame sync. When FS goes low, the serial communication port is activated. In
FS
13 13 O all serial transmission modes, FS is held low during bit transmission. Refer to
section 3 Serial Communications for detailed description.
INM
36 25 I Inverting input to analog modulator. INM requires an external RC antialias filter.
INP
35
24
I
Noninverting input to analog modulator. INP requires an external RC antialias
filter.
IGAIN
Current gain reference scaling. IGAIN is provided for decoupling of the current
45 1 O gain reference and provides a 1.35-V reference. The optimal load is a
27-K resistor.
MCLK
17
15
I
Master clock. The master clock derives the internal clocks of the sigma-delta
analog interface circuit.
MONOUT
40
28
O
Monitor output. MONOUT allows for monitoring of the analog input and is a
high-impedance output. The gain or mute is selected using Control 2 register.
OUTM
Inverting current output of the DAC. OUTM is functionally identical with and
2
6
O
complementary to OUTP. OUTM and OUTP current outputs can be loaded with
5 kΩ differentially or single-ended. This signal can also be used alone for
single-ended operation.
NOTE 1: All digital inputs and outputs are TTL-compatible, unless otherwise noted for DVDD = 5 V.
1–5