TLC320AD56 Datasheet, PDF (13/42 Pages) Texas Instruments – Sigma-Delta Analog Interface Circuit

Frame Sync and
Sampling Period
f_s
Frame-Sync Interval
ADC Channel
DAC Channel
Host
Dxx
DSxx
d
X
FIR
The time between the falling edges of successive primary frame-sync signals.
The sampling frequency that is the reciprocal of the sampling period.
The time period occupied by 16 shift clocks. It goes high on the sixteenth rising
edge of SCLK after the falling edge of the frame sync.
This term refers to all signal processing circuits between the analog input and the
digital conversion results at DOUT.
This term refers to all signal processing circuits between the digital data word
applied to DIN and the differential output analog signal available at OUTP and
OUTM.
Any processing system that interfaces to DIN, DOUT, SCLK, or FS.
Bit position in the primary data word (xx is the bit number).
Bit position in the secondary data word (xx is the bit number).
The alpha character d represents valid programmed or default data in the control
register format (see section 3.2 Secondary Serial Communications) when
discussing other data bit portions of the register.
The alpha character X represents a do-not-care bit position within the control
register format.
Finite duration impulse response.
1.7 Register Functional Summary
There are three data and control registers that are used as follows:
Register 0
The No-Op register. The 0 address allows secondary requests without altering any other
register.
Register 1 The Control 1 register. The data in this register controls:
• The software reset
• The software power down
• Selection of the normal or auxiliary analog inputs
• Selection of the digital loopback
• 16-bit or 15-bit mode of operation
• Selection of monitor amp output
Register 2 The Control 2 register. The data in this register:
• Contains the output flag indicating a decimator FIR filter overflow
• Contains Flag 0 and Flag 1 output values for use in the phone mode
• Selects the phone mode
1–7