DAC38RF82 Datasheet, PDF (38/139 Pages) Texas Instruments – Dual-Channel, Differential-Output, 14-bit, 9-GSPS, RF-Sampling DAC with JESD204B Interface, On-Chip PLL and Wide-Band Interpolation

DAC38RF82, DAC38RF89
SLASEA6 – FEBRUARY 2017
www.ti.com
8.3.12 SerDes Test Modes through Serial Programming
The DAC38RF82 (or DAC38RF89) supports a number of basic pattern generation and verification of SerDes via
the serial interface. Three pseudo random bit stream (PRBS) sequences are available, along with an alternating
0/1 pattern and a 20-bit user-defined sequence. The 2⁷ - 1, 2³¹ - 1 or 2²³ – 1 sequences implemented can often
be found programmed into standard test equipment, such as a Bit Error Rate Tester (BERT). Pattern generation
and verification selection is via field TESTPATT in register SRDS_CFG1 (8.5.86), as shown in Table 25.
TESTPATT
000
001
010
011
100
101
11x
Table 25. SerDes Test Pattern Selection
EFFECT
Test mode disabled.
Alternating 0/1 Pattern. An alternating 0/1 pattern with a period of 2 UI.
Verify 2⁷ - 1 PRBS. Uses a 7-bit LFSR with feedback polynomial x⁷ + x⁶ + 1.
Verify 2²³ - 1 PRBS. Uses an ITU O.150 conformant 23-bit LFSR with feedback polynomial x²³ + x¹⁸ + 1.
Verify 2³¹ - 1 PRBS. Uses an ITU O.150 conformant 31-bit LFSR with feedback polynomial x³¹ + x²⁸ + 1.
User-defined 20-bit pattern. Uses the USR PATT IEEE1500 Tuning instruction field to specify the pattern. The default
value is 0x66666.
Reserved.
Pattern verification compares the output of the serial to parallel converter with an expected pattern. When there
is a mismatch, the TESTFAIL bit is driven high, which can be programmed to come out the ALARM terminal by
setting field DTEST in register DTEST (8.5.76) to “0011”.
8.3.13 SerDes Test Modes through IEEE 1500 Programming
DAC38RF82 (or DAC38RF89) also provide a number of advanced diagnostic capabilities controlled by the IEEE
1500 interface. These are:
• Accumulation of pattern verification errors;
• The ability to map out the width and height of the receive eye, known as Eye Scan;
• Rreal-time monitoring of internal voltages and currents;
The SerDes blocks support the following IEEE1500 instructions:
INSTRUCTION
ws_bypass
ws_cfg
ws_core
ws_tuning
ws_debug
ws_unshadowed
ws_char
Table 26. IEEE1500 Instruction for SerDes Receivers
OPCODE
0x00
0x35
0x30
0x31
0x32
0x34
0x33
DESCRIPTION
Bypass. Selects a 1-bit bypass data register. Use when accessing other macros on the same
IEEE1500 scan chain.
Configuration. Write protection options for other instructions.
Core. Fields also accessible via dedicated core-side ports.
Tuning. Fields for fine tuning macro performance.
Debug. Fields for advanced control, manufacturing test, silicon characterization and debug.
Unshadowed. Fields for silicon characterization.
Char. Fields used for eye scan.
The data for each SerDes instruction is formed by chaining together sub-components called head, body (receiver
or transmitter) and tail. DAC38RF82 (or DAC38RF89) uses two SerDes receiver blocks R0 and R1, each of
which contains 4 receive lanes (channels), the data for each IEEE1500 instruction is formed by chaining {head,
receive lane 0, receive lane 1, receive lane 2, receive lane 3, tail}. A description of bits in head, body and tail for
each instruction is given as follows:
NOTE
All multi-bit signals in each chain are packed with bits reversed e.g. mpy[7:0] in ws_core
head subchain is packed as {retime, enpll, mpy[0:7], vrange, lb[0:1]}. All DATA REGISTER
READS from SerDes Block R0 should read 1 bit more than the desired number of bits and
discard the first bit received on TDO e.g., to read 40-bit data from R0 block, 41 bits should
be read off from TDO and the first bit received should be discarded. Similarly, any data
written to SerDes Block R0 Data Registers should be prefixed with an extra 0.
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