DAC38RF82 Datasheet, PDF (26/139 Pages) Texas Instruments – Dual-Channel, Differential-Output, 14-bit, 9-GSPS, RF-Sampling DAC with JESD204B Interface, On-Chip PLL and Wide-Band Interpolation

DAC38RF82, DAC38RF89
SLASEA6 – FEBRUARY 2017
www.ti.com
8.3.4 Serdes Equalizer
All channels of the DAC38RF82 (or DAC38RF89) incorporate an adaptive equalizer, which can compensate for
channel insertion loss by attenuating the low frequency components with respect to the high frequency
components of the signal, thereby reducing inter-symbol interference. Figure 28 shows the response of the
equalizer, which can be expressed in terms of the amount of low frequency gain and the frequency up to which
this gain is applied (i.e., the frequency of the ’zero’). Above the zero frequency, the gain increases at 6 dB/octave
until it reaches the high frequency gain.
Figure 28. Equalizer Frequency Response
The equalizer can be configured via fields EQ and EQHLD in register SRDS_CFG1 (8.5.86). Table 6 and Table 7
summarize the options. When enabled, the receiver equalization logic analyzes data patterns and transition times
to determine whether the low frequency gain should be increased or decreased. The decision logic is
implemented as a voting algorithm with a relatively long analysis interval. The slow time constant that results
reduces the probability of incorrect decisions but allows the equalizer to compensate for the relatively stable
response of the channel. The lock time for the adaptive equalizer is data dependent, and so it is not possible to
specify a generally applicable absolute limit. However, assuming random data, the maximum lock time will be
6x106 divided by the CDR activity level. For field CDR in register SRDS_CFG1 (8.5.86) = 110, the activity level
is 1.5 x 10⁶ UI.
When EQ[2] = 0, finer control of gain boost is available using the EQBOOST IEEE1500 tuning chain field, as
shown in Table 6.
EQ
00
01
[1-0]
10
11
Table 6. Receiver Equalization Configuration
EFFECT
No equalization. The equalizer provides a flat response at the maximum gain. This setting may be
appropriate if jitter at the receiver occurs predominantly as a result of crosstalk rather than
frequency dependent loss.
Fully adaptive equalization. The zero position is determined by the selected operating rate, and the
low frequency gain of the equalizer is determined algorithmically by analyzing the data patterns and
transition positions in the received data. This setting should be used for most applications.
Precursor equalization analysis. The data patterns and transition positions in the received data are
analyzed to determine whether the transmit link partner is applying more or less precursor
equalization than necessary.
Postcursor equalization analysis. The data patterns and transition positions in the received data are
analyzed to determine whether the transmit link partner is applying more or less post-cursor
equalization than necessary.
26
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89