DAC38RF82 Datasheet, PDF (110/139 Pages) Texas Instruments – Dual-Channel, Differential-Output, 14-bit, 9-GSPS, RF-Sampling DAC with JESD204B Interface, On-Chip PLL and Wide-Band Interpolation

DAC38RF82, DAC38RF89
SLASEA6 – FEBRUARY 2017
www.ti.com
8.5.71 Divided Output Clock Configuration Register (address = 0x0C) [reset = 0x8000]
Figure 121. Divided Output Clock Configuration Register (CLK_OUT)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
0
0
0
1
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 114. CLK_OUT Field Descriptions
Bit Field
15
CLK_TX_IDLE
14:13 CLK_TX_DIVSELECT
12
Reserved
11:8 CLK_TX_SWING
7:3 Reserved
2
CLK_TX_FLIP
1
TX_SYNC_ENA
0
EXTREF_ENA
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
01
0
0x0
00000
0
1
0
Description
When high puts the CLK_TX circuitry in idle mode during which
the CLKTX+ and CLKTX- output pins are driven to the proper
common-mode levels in order to charge the external AC
coupling caps. When low allows the divided clock to be driven
onto the CLKTX+ and CLKTX- output pins.
Selects either div2, div3 or div 4 output.
00 = divided by 3
01 = divided by 4
10 = divided by 2
11 = not valid
Reserved
Sets desired swing on CLKTX+ and CLKTX- outputs in mVpp-
diff
0x0 125
0x1 232
0x2 337
0x3 440
0x4 540
0x5 639
0x6 736
0x7 831
0x8 924
0x9 1012
0xA 1097
0xB 1178
0xC 1255
0xD 1329
0xE 1398
0xF 1462
Reserved
Flips the polarity of CLKTX
Syncs the CLKTX with SYSREF when asserted
Allows the chip to use an external refernce(1) or the internal
reference(0)
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