LM3S817 Datasheet, PDF (373/553 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S817 Microcontroller
11.5
Register Map
Table 11-2 on page 373 lists the UART registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that UART’s base address:
■ UART0: 0x4000.C000
■ UART1: 0x4000.D000
Note that the UART module clock must be enabled before the registers can be programmed (see
page 197). There must be a delay of 3 system clocks after the UART module clock is enabled before
any UART module registers are accessed.
Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 385)
before any of the control registers are reprogrammed. When the UART is disabled during
a TX or RX operation, the current transaction is completed prior to the UART stopping.
Table 11-2. UART Register Map
Offset Name
Type
0x000 UARTDR
0x004 UARTRSR/UARTECR
0x018 UARTFR
0x024 UARTIBRD
0x028 UARTFBRD
0x02C UARTLCRH
0x030 UARTCTL
0x034 UARTIFLS
0x038 UARTIM
0x03C UARTRIS
0x040 UARTMIS
0x044 UARTICR
0xFD0 UARTPeriphID4
0xFD4 UARTPeriphID5
0xFD8 UARTPeriphID6
0xFDC UARTPeriphID7
0xFE0 UARTPeriphID0
0xFE4 UARTPeriphID1
0xFE8 UARTPeriphID2
0xFEC UARTPeriphID3
0xFF0 UARTPCellID0
0xFF4 UARTPCellID1
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
W1C
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
Description
0x0000.0000
0x0000.0000
0x0000.0090
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0300
0x0000.0012
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0011
0x0000.0000
0x0000.0018
0x0000.0001
0x0000.000D
0x0000.00F0
UART Data
UART Receive Status/Error Clear
UART Flag
UART Integer Baud-Rate Divisor
UART Fractional Baud-Rate Divisor
UART Line Control
UART Control
UART Interrupt FIFO Level Select
UART Interrupt Mask
UART Raw Interrupt Status
UART Masked Interrupt Status
UART Interrupt Clear
UART Peripheral Identification 4
UART Peripheral Identification 5
UART Peripheral Identification 6
UART Peripheral Identification 7
UART Peripheral Identification 0
UART Peripheral Identification 1
UART Peripheral Identification 2
UART Peripheral Identification 3
UART PrimeCell Identification 0
UART PrimeCell Identification 1
See
page
375
377
379
381
382
383
385
387
389
391
392
393
395
396
397
398
399
400
401
402
403
404
July 14, 2014
373
Texas Instruments-Production Data