LMK04803_14 Datasheet, PDF (37/139 Pages) Texas Instruments – Low-Noise Clock Jitter Cleaner

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LMK04803, LMK04805, LMK04806, LMK04808
SNAS489K – MARCH 2011 – REVISED DECEMBER 2014
8.3.9.3.5.6 Other Timing Requirements
When adjusting digital delay dynamically, the falling edge of the qualifying clock selected by the
FEEDBACK_MUX must coincide with the falling edge of the clock distribution path. For this requirement to be
met, program the CLKoutX_Y_HS value of the qualifying clock group according to Table 6.
Table 6. Half Step Programming Requirement of Qualifying Clock During Sync Event
DISTRIBUTION PATH FREQUENCY
≥ 1.8 GHz
< 1.8 GHz
CLKoutX_Y_DIV VALUE
Even
Odd
Even
Odd
CLKoutX_Y_HS
Must = 1 during SYNC event.
Must = 0 during SYNC event.
Must = 0 during SYNC event.
Must = 1 during SYNC event.
8.3.9.3.5.7 Absolute Dynamic Digital Delay
Absolute dynamic digital delay can be used to program a clock output to a specific phase offset from another
clock output.
Pros:
• Simple direct phase adjustment with respect to another clock output.
• CLKoutX_Y_HS will remain constant for qualifying clock.
– Can easily use auto sync feature (SYNC_EN_AUTO = 1) when digital delay adjustment requires half step
digital delay requirements.
• Can be used with 0-delay mode.
Cons:
• For some phase adjustments there may be a glitch pulse due to SYNC assertion.
– For example see CLKout4 in Figure 11 and CLKout2 in Figure 12.
8.3.9.3.5.7.1 Absolute Dynamic Digital Delay - Example
To illustrate the absolute dynamic digital delay adjust procedure, consider the following example.
System Requirements:
• VCO Frequency = 2949.12 MHz
• CLKout0 = 983.04 MHz (CLKout0_1_DIV = 3)
• CLKout2 = 491.52 MHz (CLKout2_3_DIV = 6)
• CLKout4 = 245.76 MHz (CLKout4_5_DIV = 12)
• For all clock outputs during initial programming:
– CLKoutX_Y_DDLY = 5
– CLKoutX_Y_HS = 1
– NO_SYNC_CLKoutX_Y = 0
The application requires the 491.52 MHz clock to be stepped in 30 degree steps (~169.5 ps), which is the
minimum step resolution allowable by the clock distribution path requiring use of the half step bit
(CLKoutX_Y_HS). That is 1 / 2949.52 MHz / 2 = ~169.5 ps. During the stepping of the 491.52-MHz clock, the
983.04-MHz and 245.76-MHz clock must not be interrupted.
Step 1: The device is programmed from register R0 to R30 with values that result in the device being locked and
operating as desired, see the system requirements above. The phase of all the output clocks are aligned
because all the digital delay and half step values were the same when the SYNC was generated by
programming register R30. The timing of this is as shown in Figure 11.
Step 2: Now the registers will be programmed to prepare for changing digital delay (or phase) dynamically.
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