LMK04803_14 Datasheet, PDF (27/139 Pages) Texas Instruments – Low-Noise Clock Jitter Cleaner

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LMK04803, LMK04805, LMK04806, LMK04808
SNAS489K – MARCH 2011 – REVISED DECEMBER 2014
8.3.5.2 Entering Holdover
The holdover mode is entered as described in Input Clock Switching. Typically this is because:
• FORCE_HOLDOVER bit is set.
• PLL1 loses lock according to PLL1_DLD, and
– HOLDOVER_MODE = 2
– DISABLE_DLD1_DET = 0
• CPout1 voltage crosses DAC high or low threshold, and
– HOLDOVER_MODE = 2
– EN_VTUNE_RAIL_DET = 1
– EN_TRACK = 1
– DAC_HIGH_TRIP = User Value
– DAC_LOW_TRIP = User Value
– EN_MAN_DAC = 1
– MAN_DAC = User Value
8.3.5.3 During Holdover
PLL1 is run in open loop mode.
• PLL1 charge pump is set to TRI-STATE.
• PLL1 DLD will be unasserted.
• The HOLDOVER status is asserted
• During holdover If PLL2 was locked prior to entry of holdover mode, PLL2 DLD will continue to be asserted.
• CPout1 voltage will be set to:
– a voltage set in the MAN_DAC register (fixed CPout1).
– a voltage determined to be the last valid CPout1 voltage (tracked CPout1).
• PLL1 DLD will attempt to lock with the active clock input.
The HOLDOVER status signal can be monitored on the Status_HOLDOVER or Status_LD pin by programming
the HOLDOVER_MUX or LD_MUX register to "Holdover Status."
8.3.5.4 Exiting Holdover
Holdover mode can be exited in one of two ways.
• Manually, by programming the device from the host.
• Automatically, By a clock operating within a specified ppm of the current PLL1 frequency on the active clock
input. See Input Clock Switching for more detail on which clock input is active.
To exit holdover by programming, set HOLDOVER_MODE = Disabled. HOLDOVER_MODE can then be re-
enabled by programming HOLDOVER_MODE = Enabled. Care should be taken to ensure that the active clock
upon exiting holdover is as expected, otherwise the CLKin_SELECT_MODE register may need to be re-
programmed.
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