LMK04803_14 Datasheet, PDF (1/139 Pages) Texas Instruments – Low-Noise Clock Jitter Cleaner

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LMK04803, LMK04805, LMK04806, LMK04808
SNAS489K – MARCH 2011 – REVISED DECEMBER 2014
LMK0480x Low-Noise Clock Jitter Cleaner with Dual Loop PLLs
1 Features
•1 Ultra-Low RMS Jitter Performance
– 111 fs RMS Jitter (12 kHz to 20 MHz)
– 123 fs RMS Jitter (100 Hz to 20 MHz)
• Dual Loop PLLatinum™ PLL Architecture
• PLL1
– Integrated Low-Noise Crystal Oscillator Circuit
– Holdover Mode when Input Clocks are Lost
– Automatic or Manual Triggering/Recovery
• PLL2
– Normalized PLL Noise Floor of –227 dBc/Hz
– Phase Detector Rate up to 155 MHz
– OSCin Frequency-Doubler
– Integrated Low-Noise VCO
• 2 Redundant Input Clocks with LOS
– Automatic and Manual Switch-Over Modes
• 50 % Duty Cycle Output Divides, 1 to 1045 (Even
and Odd)
• 12 LVPECL, LVDS, or LVCMOS Programmable
Outputs
• Digital Delay: Fixed or Dynamically Adjustable
• 25 ps Step Analog Delay Control.
• 14 Differential Outputs. Up to 26 Single Ended.
– Up to 6 VCXO/Crystal Buffered Outputs
• Clock Rates of up to 1536 MHz
• 0-Delay Mode
• Three Default Clock Outputs at Power Up
• Multi-Mode: Dual PLL, Single PLL, and Clock
Distribution
• Industrial Temperature Range: –40 to 85°C
• 3.15-V to 3.45-V Operation
• 2 Dedicated Buffered/Divided OSCin Clocks
• Package: 64-Pin WQFN (9.0 × 9.0 × 0.8 mm)
2 Applications
• Data Converter Clocking
• Wireless Infrastructure
• Networking, SONET/SDH, DSLAM
• Medical / Video / Military / Aerospace
• Test and Measurement
3 Description
The LMK0480x family is the industry's highest
performance clock conditioner with superior clock
jitter cleaning, generation, and distribution with
advanced features to meet next generation system
requirements. The dual loop PLLatinum™
architecture is capable of 111 fs rms jitter (12 kHz to
20 MHz) using a low noise VCXO module or sub-200
fs rms jitter (12 kHz to 20 MHz) using a low cost
external crystal and varactor diode.
The dual loop architecture consists of two high-
performance phase-locked loops (PLL), a low-noise
crystal oscillator circuit, and a high-performance
voltage controlled oscillator (VCO). The first PLL
(PLL1) provides low-noise jitter cleaner functionality
while the second PLL (PLL2) performs the clock
generation. PLL1 can be configured to either work
with an external VCXO module or the integrated
crystal oscillator with an external tunable crystal and
varactor diode. When paired with a very narrow loop
bandwidth, PLL1 uses the superior close-in phase
noise (offsets below 50 kHz) of the VCXO module or
the tunable crystal to clean the input clock. The
output of PLL1 is used as the clean input reference to
PLL2 where it locks the integrated VCO. The loop
bandwidth of PLL2 can be optimized to clean the far-
out phase noise (offsets above 50 kHz) where the
integrated VCO outperforms the VCXO module or
tunable crystal used in PLL1.
PART NUMBER
LMK04803
LMK04805
LMK04806
LMK04808
Device Information
VCO FREQUENCY
1840 to 2030 MHz
2148 to 2370 MHz
2370 to 2600 MHz
2750 to 3072 MHz
REFERENCE
INPUTS
2
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic
Recovered
³GLUW\´FORFNRU
clean clock
Crystal or
VCXO
CLKin0
OSCout0/
OSCout1
CLKout0, 1
LMX2541
PLL+VCO
Backup
Reference
Clock
CLKin1
I
LMK0480x
Precision Clock
Conditioner
CLKout2
CLKout3
CLKout4, 5, 6, 7
FFPPGGAA
CLKout11
CLKout8A
IF
CLKout9
Q
CPLD
ADC
0XOWLSOH³FOHDQ´
clocks at different
frequencies
Serializer/
Deserializer
DDAACC
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.