AM5718-HIREL Datasheet, PDF (364/396 Pages) Texas Instruments – Sitara Processors Silicon Revision 2.0

AM5718-HIREL
SPRS999 – AUGUST 2017
www.ti.com
(1) This is the absolute maximum the clock period can be. Actual maximum clock period may be limited by DDR3 speed grade and
operating frequency (see the DDR3 memory device data sheet).
1
DDR_CLK
SPRS906_PCB_DDR3_01
Figure 8-1. DDR3 Memory Controller Clock Timing
8.2.2.2 DDR3 EMIF
The processor contains one DDR3 EMIF.
8.2.2.3 DDR3 Device Combinations
Because there are several possible combinations of device counts and single- or dual-side mounting,
Table 8-4 summarizes the supported device configurations.
Table 8-4. Supported DDR3 Device Combinations
NUMBER OF DDR3 DEVICES DDR3 DEVICE WIDTH (BITS)
MIRRORED?
DDR3 EMIF WIDTH (BITS)
1
16
N
16
2
8
Y⁽¹⁾
16
2
16
N
32
2
16
Y⁽¹⁾
32
3
16
N ⁽³⁾
32
4
8
N
32
4
8
Y⁽²⁾
32
5
8
N ⁽³⁾
32
(1) Two DDR3 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of
the board.
(2) This is two mirrored pairs of DDR3 devices.
(3) Three or five DDR3 device combination is not available on this device, but combination types are retained for consistency with the
AM57xx family of devices.
8.2.2.4 DDR3 Interface Schematic
8.2.2.4.1 32-Bit DDR3 Interface
The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used and the width
of the bus used (16 or 32 bits). General connectivity is straightforward and very similar. 16-bit DDR
devices look like two 8-bit devices. Figure 8-2 and Figure 8-3 show the schematic connections for 32-bit
interfaces using x16 devices.
8.2.2.4.2 16-Bit DDR3 Interface
Note that the 16-bit wide interface schematic is practically identical to the 32-bit interface (see Figure 8-2
and Figure 8-3); only the high-word DDR memories are removed and the unused DQS inputs are tied off.
When not using all or part of a DDR interface, the proper method of handling the unused pins is to tie off
the ddrx_dqsi pins to ground via a 1k-Ω resistor and to tie off the ddrx_dqsni pins to the corresponding
vdds_ddrx supply via a 1k-Ω resistor. This needs to be done for each byte not used. Although these
signals have internal pullups and pulldowns, external pullups and pulldowns provide additional protection
against external electrical noise causing activity on the signals.
The vdds_ddrx and ddrx_vref0 power supply pins need to be connected to their respective power supplies
even if ddrx is not being used. All other DDR interface pins can be left unconnected. Note that the
supported modes for use of the DDR EMIF are 32-bits wide, 16-bits wide, or not used.
364 Applications, Implementation, and Layout
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