AM5718-HIREL Datasheet, PDF (153/396 Pages) Texas Instruments – Sitara Processors Silicon Revision 2.0

www.ti.com
AM5718-HIREL
SPRS999 – AUGUST 2017
Table 5-9. Maximum Supported Frequency (continued)
MODULE
Instance Name Input Clock Name
GPU
GPU_FCLK1
GPU_FCLK2
HDMI PHY
HDQ1W
GPU_ICLK
DSS_HDMI_PHY_
CLK
HDQ1W_ICLK
I2C1
I2C2
I2C3
I2C4
I2C5
IEEE1500_2_OCP
HDQ1W_FCLK
I2C1_ICLK
I2C1_FCLK
I2C2_ICLK
I2C2_FCLK
I2C3_ICLK
I2C3_FCLK
I2C4_ICLK
I2C4_FCLK
I2C5_ICLK
I2C5_FCLK
PI_L3CLK
IPU1
IPU1_GFCLK
IPU2
IVA
KBD
L3_INSTR
L3_MAIN
L4_CFG
L4_PER1
L4_PER2
L4_PER3
L4_WKUP
IPU2_GFCLK
IVA_GCLK
KBD_FCLK
PICLKKBD
KBD_ICLK
PICLKOCP
L3_CLK
L3_CLK1
L3_CLK2
L4_CFG_CLK
L4_PER1_CLK
L4_PER2_CLK
L4_PER3_CLK
L4_WKUP_CLK
Clock
Type
Func
Func
Int
Func
Int &
Func
Func
Int
Func
Int
Func
Int
Func
Int
Func
Int
Func
Int &
Func
Int &
Func
Int &
Func
Int
Func
Func
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Max. Clock
Allowed (MHz)
GPU_CLK
GPU_CLK
266
38.4
CLOCK SOURCES
PRCM Clock Name
PLL / OSC /
Source Clock
Name
GPU_CORE_GCLK CORE_GPU_CLK
PER_GPU_CLK
GPU_GCLK
GPU_HYD_GCLK CORE_GPU_CLK
PER_GPU_CLK
GPU_GCLK
GPU_L3_GICLK
CORE_X2_CLK
HDMI_PHY_GFCLK FUNC_192M_CLK
266
L4PER_L3_GICLK
CORE_X2_CLK
12
PER_12M_GFCLK FUNC_192M_CLK
266
L4PER_L3_GICLK
CORE_X2_CLK
96
PER_96M_GFCLK FUNC_192M_CLK
266
L4PER_L3_GICLK
CORE_X2_CLK
96
PER_96M_GFCLK FUNC_192M_CLK
266
L4PER_L3_GICLK
CORE_X2_CLK
96
PER_96M_GFCLK FUNC_192M_CLK
266
L4PER_L3_GICLK
CORE_X2_CLK
96
PER_96M_GFCLK FUNC_192M_CLK
266
IPU_L3_GICLK
CORE_X2_CLK
96
IPU_96M_GFCLK FUNC_192M_CLK
266
L3INIT_L3_GICLK
CORE_X2_CLK
425.6
425.6
IVA_GCLK
0.032
0.032
38.4
38.4
L3_CLK
L3_CLK
L3_CLK
133
133
133
133
38.4
IPU1_GFCLK
DPLL_ABE_X2_CL
K
CORE_IPU_ISS_B
OOST_CLK
IPU2_GFCLK
CORE_IPU_ISS_B
OOST_CLK
IVA_GCLK
IVA_GFCLK
WKUPAON_SYS_GFC WKUPAON_32K_G
LK
FCLK
WKUPAON_SYS_GFC
LK
WKUPAON_GICLK
SYS_CLK1
WKUPAON_GICLK DPLL_ABE_X2_CL
K
L3INSTR_L3_GICLK CORE_X2_CLK
L3MAIN1_L3_GICLK CORE_X2_CLK
L3INSTR_L3_GICLK CORE_X2_CLK
L4CFG_L3_GICLK
CORE_X2_CLK
L4PER_L3_GICLK
CORE_X2_CLK
L4PER2_L3_GICLK CORE_X2_CLK
L4PER3_L3_GICLK CORE_X2_CLK
WKUPAON_GICLK
SYS_CLK1
DPLL_ABE_X2_CL
K
PLL / OSC /
Source Name
DPLL_CORE
DPLL_PER
DPLL_GPU
DPLL_CORE
DPLL_PER
DPLL_GPU
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_ABE
DPLL_CORE
DPLL_CORE
DPLL_IVA
OSC1
RTC Oscillator
OSC1
DPLL_ABE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
OSC1
DPLL_ABE
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: AM5718-HIREL
Specifications 153