AM5718-HIREL Datasheet, PDF (283/396 Pages) Texas Instruments – Sitara Processors Silicon Revision 2.0

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AM5718-HIREL
SPRS999 – AUGUST 2017
Table 7-59. Virtual Mode Case Details for McASP8 (continued)
No.
CASE
CASE
Description
Virtual Mode Settings
Signals
Virtual Mode Value
Notes
4
CIOFOI
CLKR / FSX:
AXR(Outputs)/CLKX/FSX
MCASP8_VIRTUAL1_SYNC_RX
See Figure 7-46
Output CLKX
/ FSR: Input
AXR(Inputs)/CLKR/FSR
MCASP8_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
CO-FO- CLKX / FSX:
AXR(Outputs)/CLKX/FSX
Output
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See Figure 7-47
6
CI-FO-
FSX: Output
AXR(Outputs)/CLKX/FSX
MCASP8_VIRTUAL1_SYNC_RX
See Figure 7-48
CLKX: Input
AXR(Inputs)/CLKX/FSX
MCASP8_VIRTUAL1_SYNC_RX
7
CI-FI-
CLKX / FSX:
AXR(Outputs)/CLKX/FSX
MCASP8_VIRTUAL1_SYNC_RX
See Figure 7-49
Input
AXR(Inputs)/CLKX/FSX
MCASP8_VIRTUAL1_SYNC_RX
8
CO-FI-
CLKX:
AXR(Outputs)/CLKX/FSX
Output FSX:
Input
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See Figure 7-50
McASP
SoC IOs
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
Figure 7-43. McASP1-8 COIFOI - ASYNC Mode
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Timing Requirements and Switching Characteristics 283
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