AM5718-HIREL Datasheet, PDF (348/396 Pages) Texas Instruments – Sitara Processors Silicon Revision 2.0

AM5718-HIREL
SPRS999 – AUGUST 2017
www.ti.com
Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS1 PRU1 Direct
Input mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO Timings
Modes. See Table 7-156 Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Input mode for a
definition of the Manual modes.
Table 7-156 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
BALL
D3
F6
D5
C2
C3
C4
B2
D6
C5
A3
B3
B4
B5
A4
E2
D2
F4
C1
E4
F5
E6
Table 7-156. Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Input mode
BALL NAME
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
vin2a_d3
vin2a_d4
vin2a_d5
vin2a_d6
vin2a_d7
vin2a_d8
vin2a_d9
PR1_PRU1_DIR_IN_MANUAL
A_DELAY (ps)
G_DELAY (ps)
0
800
0
0
0
200
0
0
0
0
0
400
0
300
0
400
0
900
0
1500
0
100
0
500
0
500
0
600
0
900
0
100
0
600
0
200
0
400
0
500
0
600
CFG REGISTER
CFG_VIN2A_D10_IN
CFG_VIN2A_D11_IN
CFG_VIN2A_D12_IN
CFG_VIN2A_D13_IN
CFG_VIN2A_D14_IN
CFG_VIN2A_D15_IN
CFG_VIN2A_D16_IN
CFG_VIN2A_D17_IN
CFG_VIN2A_D18_IN
CFG_VIN2A_D19_IN
CFG_VIN2A_D20_IN
CFG_VIN2A_D21_IN
CFG_VIN2A_D22_IN
CFG_VIN2A_D23_IN
CFG_VIN2A_D3_IN
CFG_VIN2A_D4_IN
CFG_VIN2A_D5_IN
CFG_VIN2A_D6_IN
CFG_VIN2A_D7_IN
CFG_VIN2A_D8_IN
CFG_VIN2A_D9_IN
MUXMODE
12
pr1_pru1_gpi7
pr1_pru1_gpi8
pr1_pru1_gpi9
pr1_pru1_gpi10
pr1_pru1_gpi11
pr1_pru1_gpi12
pr1_pru1_gpi13
pr1_pru1_gpi14
pr1_pru1_gpi15
pr1_pru1_gpi16
pr1_pru1_gpi17
pr1_pru1_gpi18
pr1_pru1_gpi19
pr1_pru1_gpi20
pr1_pru1_gpi0
pr1_pru1_gpi1
pr1_pru1_gpi2
pr1_pru1_gpi3
pr1_pru1_gpi4
pr1_pru1_gpi5
pr1_pru1_gpi6
Manual IO Timings Modes must be used to guaranteed some IO timings for PRU-ICSS1 PRU1 Direct
Output mode. See Table 7-2 Modes Summary for a list of IO timings requiring the use of Manual IO
Timings Modes. See Table 7-157 Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Output mode
for a definition of the Manual modes.
Table 7-157 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
BALL
D3
F6
D5
C2
C3
C4
B2
D6
Table 7-157. Manual Functions Mapping for PRU-ICSS1 PRU1 Direct Output mode
BALL NAME
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
PR1_PRU1_DIR_OUT_MANUAL
A_DELAY (ps)
G_DELAY (ps)
0
1000
0
1300
0
2300
0
2200
0
1800
0
1800
0
1600
0
2000
CFG REGISTER
CFG_VIN2A_D10_OUT
CFG_VIN2A_D11_OUT
CFG_VIN2A_D12_OUT
CFG_VIN2A_D13_OUT
CFG_VIN2A_D14_OUT
CFG_VIN2A_D15_OUT
CFG_VIN2A_D16_OUT
CFG_VIN2A_D17_OUT
MUXMODE
13
pr1_pru1_gpo7
pr1_pru1_gpo8
pr1_pru1_gpo9
pr1_pru1_gpo10
pr1_pru1_gpo11
pr1_pru1_gpo12
pr1_pru1_gpo13
pr1_pru1_gpo14
348 Timing Requirements and Switching Characteristics
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