TMS320TCI6612 Datasheet, PDF (36/250 Pages) Texas Instruments – Communications Infrastructure KeyStone SoC

TMS320TCI6612
Communications Infrastructure KeyStone SoC
SPRS784B—November 2011
2.5.2.6 SPI Boot Device Configuration
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In SPI boot mode, the SPI device configuration uses ten bits of device configuration instead of seven as used in other
boot modes.
Figure 2-9 SPI Device Configuration Fields
13
12
11
10
9
8
7
6
5
4
Mode
4, 5 Pin
Addr Width
Chip Select
Parameter Table Index
Reserved
Table 2-11 SPI Device Configuration Field Descriptions
Bit
13-12
Field
Mode
11
4, 5 Pin
10
Addr Width
9-8
Chip Select
7-6
Parameter Table Index
5-4
Reserved
End of Table 2-11
Description
Clk Pol / Phase
0 = Data is output on the rising edge of SPICLK. Input data is latched on the falling edge.
1 = Data is output one half-cycle before the first rising edge of SPICLK and on subsequent falling edges. Input
data is latched on the rising edge of SPICLK.
2 = Data is output on the falling edge of SPICLK. Input data is latched on the rising edge.
3 = Data is output one half-cycle before the first falling edge of SPICLK and on subsequent rising edges. Input
data is latched on the falling edge of SPICLK.
Selects the operational mode
0 = 4-pin mode used
1 = 5-pin mode used
Selects the SPI address width
0 = 16-bit address values are used
1 = 24-bit address values are used
The chip select field value
This value can range from 0 to 3.
Specifies which parameter table is loaded
This value can range from 0 to 3
Reserved
2.5.2.7 HyperLink Boot Device Configuration
Figure 2-10 HyperLink Boot Device Configuration Fields
10
9
8
7
6
Reserved
Data Rate
Ref Clock
5
4
Reserved
Table 2-12 HyperLink Boot Device Configuration Field Descriptions
Bit Field
10 Reserved
9-8 Data Rate
7-6 Ref Clocks
5-4 Reserved
End of Table 2-12
Description
Reserved
Selects the line rate for each link
0 = 1.25 GBs
1 = 3.125 GBs
2 = 6.25 GBs
3 = 12.5 GBs
Selects the reference clock input
0 = 156.25 MHz
1 = 250 MHz
2 = 312.5 MHz
Reserved
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