TMS320TCI6612 Datasheet, PDF (132/250 Pages) Texas Instruments – Communications Infrastructure KeyStone SoC

TMS320TCI6612
Communications Infrastructure KeyStone SoC
SPRS784B—November 2011
www.ti.com
Table 8-9 explains further the types of reset, the reset initiator, and the effects of each reset on the device. For more
information on the effects of each reset on the PLL controllers and their clocks, see Section 8.5.7 ‘‘Reset Electrical
Data/Timing’’ on page 136.
Table 8-9
Reset Types
Type
Initiator
Effect(s)
Power-on reset
POR pin
RESETFULL pin
Resets the entire chip including the test and emulation logic and ARM Subsystem. The device
configuration pins are latched only during power-on reset.
Hard reset
RESET pin
PLLCTL ⁽¹⁾ register (RSCTRL)
Watchdog timers
Emulation
Hard reset resets everything except for the ARM interrupt controller, test, emulation logic and
reset isolation modules. This reset is also different from power-on reset in that the PLLCTL assumes
power and clocks are stable when hard reset is asserted. The device configurations pins are not
re-latched.
Emulation initiated reset is always a hard reset.
By default these initiators are configured as hard reset, but can be configured (except emulation)
as soft reset in the RSCFG register of PLLCTL. Contents of DDR3 SDRAM memory can be retained
during a hard reset if the SDRAM is placed in self-refresh mode.
Soft reset
RESET pin
PLLCTL register (RSCTRL)
Watchdog timers
Soft reset will behave like hard reset except that PCIe MMRs (memory-mapped registers) and
DDR3 EMIF MMRs contents are retained.
By default these initiators are configured as hard reset, but can be configured as soft reset in the
RSCFG register of PLLCTL. Contents of DDR3 SDRAM memory can be retained during a soft reset if
the SDRAM is placed in self-refresh mode.
Local reset
End of Table 8-9
LRESET pin
Watchdog timer timeout
LPSC MMRs
Resets the CorePac, without disturbing clock alignment or memory contents. The device
configuration pins are not re-latched.
1 All masters in the device have access to the PLLCTL registers.
8.5.1 Power-on Reset
Power-on reset is used to reset the entire device, including the test and emulation logic.
Power-on reset is initiated by the following
1. POR pin
2. RESETFULL pin
During power-up, the POR pin must be asserted (driven low) until the power supplies have reached their normal
operating conditions. A RESETFULL pin is also provided to allow the on-board host to reset the entire device
including the reset isolated logic. The assumption is that, device is already powered up and hence unlike POR,
RESETFULL pin will be driven by the on-board host control other than the power good circuitry. For power-on
reset, the Main PLL controller comes up in bypass mode and the PLL is not enabled. Other resets do not affect the
state of the PLL or the dividers in the PLL controller.
The following sequence must be followed during a power-on reset:
1. Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted (driven
low). While POR is asserted, all pins except RESETSTAT will be set to high-impedance. After the POR pin is
de-asserted (driven high), all Z group pins, low group pins, and high group pins are set to their reset state and
will remain at their reset state until otherwise configured by their respective peripheral. All peripherals that are
power managed, are disabled after a Power-on reset and must be enabled through the Device State Control
registers (for more details, see Section Table 3-2 ‘‘Device State Control Registers’’ on page 75).
2. Clocks are reset, and they are propagated throughout the chip to reset any logic that was using reset
synchronously. All logic is now reset and RESETSTAT will be driven low indicating that the device is in reset.
3. POR must be held active until all supplies on the board are stable then for at least an additional time for the
Chip level PLLs to lock.
132 TMS320TCI6612 Peripheral Information and Electrical Specifications
Copyright 2011 Texas Instruments Incorporated