 English |
|
|
|
|
|
|
|
| TMS320TCI6612 Datasheet, PDF (223/250 Pages) Texas Instruments – Communications Infrastructure KeyStone SoC | |||
| |||
| ◁ |
www.ti.com
Figure 8-35 shows a block diagram of the I2C module.
Figure 8-35 I2C Module Block Diagram
TMS320TCI6612
Communications Infrastructure KeyStone SoC
SPRS784BâNovember 2011
I2C Module
Clock
Prescale
I2CPSC
Peripheral Clock
(CPU/6)
SCL
I2C Clock
Noise
Filter
SDA
I2C Data
Noise
Filter
Bit Clock
Generator
I2CCLKH
I2CCLKL
Transmit
I2CXSR
Transmit
Shift
I2CDXR
Transmit
Buffer
Receive
I2CDRR
Receive
Buffer
I2CRSR
Receive
Shift
Control
I2COAR
I2CSAR
Own
Address
Slave
Address
I2CMDR Mode
I2CCNT
I2CEMDR
Data
Count
Extended
Mode
Interrupt/DMA
I2CIMR
I2CSTR
I2CIVR
Interrupt
Mask/Status
Interrupt
Status
Interrupt
Vector
Shading denotes control/status registers.
8.13.2 I2C Peripheral Register Description(s)
Table 8-82 I2C Registers (Part 1 of 2)
Hex Address Range
0253 0000
0253 0004
0253 0008
0253 000C
0253 0010
0253 0014
0253 0018
0253 001C
0253 0020
0253 0024
0253 0028
0253 002C
0253 0030
Field
ICOAR
ICIMR
ICSTR
ICCLKL
ICCLKH
ICCNT
ICDRR
ICSAR
ICDXR
ICMDR
ICIVR
ICEMDR
ICPSC
Register Name
I2C own address register
I2C interrupt mask/status register
I2C interrupt status register
I2C clock low-time divider register
I2C clock high-time divider register
I2C data count register
I2C data receive register
I2C slave address register
I2C data transmit register
I2C mode register
I2C interrupt vector register
I2C extended mode register
I2C prescaler register
Copyright 2011 Texas Instruments Incorporated
TMS320TCI6612 Peripheral Information and Electrical Specifications 223
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese