TMS320TCI6612 Datasheet, PDF (242/250 Pages) Texas Instruments – Communications Infrastructure KeyStone SoC

TMS320TCI6612
Communications Infrastructure KeyStone SoC
SPRS784B—November 2011
Figure 8-54 AIF2 RP1 Frame Synchronization Clock Timing
RP1CLKN
1
2
3
RP1CLKP
4
5
Figure 8-55
RP1CLKN
RP1CLKP
AIF2 RP1 Frame Synchronization Burst Timing
6
www.ti.com
RP1FBP/N
7
RP1 Frame Burst BIT 0
8
RP1 Frame Burst BIT 2
9
Figure 8-56
AIF2 Physical Layer Synchronization Pulse Timing
11
10
PHYSYNC
RP1 Frame Burst BIT N
Figure 8-57
AIF2 Radio Synchronization Pulse Timing
13
12
RADSYNC
Table 8-101 AIF2 Timer Module Switching Characteristics
(see Figure 8-58)
No.
14 tw(EXTFRAMEEVENTH)
15 tw(EXTFRAMEEVENTL)
End of Table 8-101
Parameter
External Frame Event
Pulse width, EXTFRAMEEVENT output high
Pulse width, EXTFRAMEEVENT output low
1 C1 = tc(RP1CLKN/P)
Figure 8-58 AIF2 Timer External Frame Event Timing
14
15
EXT FRAME EVENT
Min
Max
Unit
4 * C1 ⁽¹⁾
ns
4 * C1
ns
242 TMS320TCI6612 Peripheral Information and Electrical Specifications
Copyright 2011 Texas Instruments Incorporated