ADS8327_14 Datasheet, PDF (36/51 Pages) Texas Instruments – LOW POWER, 16-BIT, 500-kHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE

ADS8327
ADS8328
SLAS415E – APRIL 2006 – REVISED JANUARY 2011
www.ti.com
SCLK skew between converters and data path delay through the converters configured in chain mode can affect
the maximum frequency of SCLK. The delay can also be affected by supply voltage and loading. It may be
necessary to slow down the SCLK when the devices are configured in chain mode.
ADS 8327 # 3
CDI
Logic
Delay
Plus PAD
2.7 ns
D
Logic
Delay
Q
< = 8 .3 ns
CLK
SDO
Logic
Delay
Plus PAD
8.3 ns
Serial data
output
CDI
Logic
Delay
Plus PAD
2.7 ns
D
Logic
Delay
Q
< = 8 .3 ns
CLK
ADS 8327 # 2
SDO
Logic
Delay
Plus PAD
8.3 ns
Serial data
input
CDI
Logic
Delay
Plus PAD
2.7 ns
D
Logic
Delay
Q
< = 8 .3 ns
CLK
ADS 8327 # 1
SDO
Logic
Delay
Plus PAD
8.3 ns
SCLK input
Figure 63. Typical Delay Through Converters Configured in Chain Mode
RESET
The converter has two reset mechanisms, a power-on reset (POR) and a software reset using CFR_D0. These
two mechanisms are NOR-ed internally. When a reset (software or POR) is issued, all register data are set to the
default values (all 1s) and the SDO output (during the cycle immediately after reset) is set to all 1s. The state
machine is reset to the power-on state.
SW RESET
POR
CDI
SET
Conversion Clock
SAR Shift
Register
EOC
Intermediate
Latch
Latched by End Of
Conversion
Output
Register
SDO
SCLK
Latched by Falling Edge of CS
CS
EOC
Figure 64. Digital Output Under Reset Condition
36
Submit Documentation Feedback
Product Folder Link(s): ADS8327 ADS8328
© 2006–2011, Texas Instruments Incorporated