ADS8327_14 Datasheet, PDF (24/51 Pages) Texas Instruments – LOW POWER, 16-BIT, 500-kHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE

ADS8327
ADS8328
SLAS415E – APRIL 2006 – REVISED JANUARY 2011
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Manual Channel Select Mode
The conversion cycle starts with selecting an acquisition channel by writing a channel number to the command
register (CMR). This cycle time can be as short as 4 serial clocks (SCLK).
Auto Channel Select Mode
Channel selection can also be done automatically if auto channel select mode is enabled. This is the default
channel select mode. The dual channel converter, ADS8328, has a built-in 2-to-1 MUX. If the device is
programmed for auto channel select mode then signals from channel 0 and channel 1 are acquired with a fixed
order. Channel 0 is accessed first in the next cycle after the command cycle that configured CFR_D11 to 1 for
auto channel select mode. This automatic access stops the cycle after the command cycle that sets CFR_D11 to
'0'.
Start of a Conversion
The end of acquisition or sampling instance (EOS) is the same as the start of a conversion. This is initiated by
bringing the CONVST pin low for a minimum of 40 ns. After the minimum requirement has been met, the
CONVST pin can be brought high. CONVST acts independent of FS/CS so it is possible to use one common
CONVST for applications requiring simultaneous sample/hold with multiple converters. The ADS8327/28
switches from sample to hold mode on the falling edge of the CONVST signal. The ADS8327/28 requires 18
conversion clock (CCLK) edges to complete a conversion. The conversion time is equivalent to 1500 ns with a
12-MHz internal clock. The minimum time between two consecutive CONVST signals is 21 CCLKs.
A conversion can also be initiated without using CONVST if it is so programmed (CFR_D9 = 0). When the
converter is configured as auto trigger, the next conversion is automatically started three conversion clocks
(CCLK) after the end of a conversion. These three conversion clocks (CCLK) are used as the acquisition time. In
this case the time to complete one acquisition and conversion cycle is 21 CCLKs.
Table 2. Different Types of Conversion
MODE
SELECT CHANNEL
Auto Channel Select⁽¹⁾
Automatic _{No need to write channel number to the CMR. Use internal sequencer for the}
ADS8328.
Manual
Manual Channel Select
Write the channel number to the CMR.
START CONVERSION
Auto Trigger
Start a conversion based on the conversion
clock CCLK.
Manual Trigger
Start a conversion with CONVST.
(1) Auto channel select should be used with auto trigger and also with the TAG bit enabled.
Status Output EOC/INT
When the status pin is programmed as EOC and the polarity is set as active low, the pin works in the following
manner: The EOC output goes LOW immediately following CONVST going LOW when manual trigger is
programmed. EOC stays LOW throughout the conversion process and returns to HIGH when the conversion has
ended. The EOC output goes low for three conversion clocks (CCLK) after the previous rising edge of EOC, if
auto trigger is programmed.
This status pin is programmable. It can be used as an EOC output (CFR.D[7:6] = 1, 1) where the low time is
equal to the conversion time. This status pin can be used as INT. (CFR.D[7:6] = 1, 0) which is set LOW at the
end of a conversion is brought to HIGH (cleared) by the next read cycle. The polarity of this pin, used as either
function (EOC or INT), is programmable through CFR_D7.
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