OMAP5910JGDY2 Datasheet, PDF (35/171 Pages) Texas Instruments – Dual-Core Processor

Introduction
Table 2--4. Signal Description (Continued)
SIGNAL
GZG GDY
BALL BALL
DESCRIPTION
TYPE^†
EMIFF SDRAM Interface (Continued)
SDRAM.A[12:0]
G10, C8, SDRAM address bus. Provides row and column address information to the
O/Z
H10, B9, SDRAM memory as well as MRS command data. SDRAM.A[10] also serves as a
C11, E9, control signal to define specific commands to SDRAM memory.
D11, A8,
G11, C10,
C12, F9,
D12, D9,
H11, A9,
C13, D10,
D13, C11,
G12, B10,
C14, A10,
B14 B11
EMIFS FLASH and Asynchronous Memory Interface
FLASH.WP
V4 R3 EMIFS write protect. Active-low output for hardware write protection feature on
O/Z
standard memory devices.
FLASH.WE
W2 P2 EMIFS write enable. Active-low write enable output for Flash or SRAM memories
O/Z
or asynchronous devices.
FLASH.RP
W1 T2
EMIFS power down or reset output (Intel™ flash devices)
O/Z
FLASH.OE
U4 N3 EMIFS output enable. Active-low output enable output for Flash or SRAM
O/Z
memories or asynchronous devices.
FLASH.D[15:0]
V3, U2, EMIFS data bus. Bidirectional 16-bit data bus used to transfer read and write data I/O/Z
T4, T1, during EMIFS accesses.
U3, N2,
U1, R1,
P8, M3,
T3, P1,
T2, N1,
R4, N4,
R3, M5,
R2, M4,
P7, M2,
P4, M1,
P2, L6,
N7, L4,
N2, K3,
N4 L5
FLASH.CLK
N3 K4 EMIFS clock. Clock output that is active during synchronous modes of EMIFS
O/Z
operation for synchronous burst Flash memories.
FLASH.CS3
FLASH.CS2
FLASH.CS1
FLASH.CS0
N8 L1
M4 K5
M3 K1
M7 J2
EMIFS chip selects. Active-low chip-select outputs that become active when the
O/Z
appropriate address is decoded internal to the device. Each chip select decodes a
32M-byte region of memory space.
FLASH.BE[1:0]
M8, J1, EMIFS byte enables. Active-low byte enable signals used to perform byte-wide
O/Z
L3
J5
accesses to memories or devices that support byte enables.
FLASH.ADV
L4
H1 EMIFS address valid. Active-low control signal used to indicate a valid address is
O/Z
present on the FLASH.A[24:1] bus.
FLASH.BAA
M4 K5
EMIFS burst advance acknowledge. Active-low control signal used with Advanced O/Z
Micro Devices™ burst Flash. FLASH.BAA is multiplexed with FLASH.CS2.
† _{I = Input, O = Output, Z = High-Impedance}
‡ _{All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain}
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§ _{See Sections 5.6.1 and 5.6.2 for special VSS considerations with oscillator circuits.}
Intel is a registered trademark of Intel Corporation.
Advanced Micro Devices is a trademark of Advanced Micro Devices, Inc.
August 2002 -- Revised August 2004
SPRS197D
35