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OMAP5910JGDY2 Datasheet, PDF (151/171 Pages) Texas Instruments – Dual-Core Processor | |||
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Electrical Specifications
5.11 Camera Interface Timings
Table 5--26 assumes testing over recommended operating conditions (see Figure 5--26).
Table 5--26. Camera Interface Timing Requirements
NO.
MIN
MAX UNIT
C1 1 / [ tc(LCKH--HSV) ]
Operating frequency, CAM.LCLK
13 MHz
C2 1 / [ tc(XCKH--HSV) ]
Operating frequency, CAM.EXCLK
24 MHz
C3
tw(LCK)
Pulse duration, CAM.LCLK high or low
0.45Pâ
0.55Pâ ns
C5
tsu(LCKH--DV)
Setup time, CAM.D[7:0] data valid before CAM.LCLK high
1â¡
ns
C6
th(DV--LCKH)
Hold time, CAM.D[7:0] data valid after CAM.LCLK high
9â¡
ns
C7
tsu(LCKH--DV)
Setup time, CAM.VS/CAM.HS active before CAM.LCLK high
1â¡
ns
C8
th(DV--CLKH)
Hold time, CAM.VS/CAM.HS active after CAM.LCLK high
9â¡
ns
â P = period of CAM.LCLK in nanoseconds (ns).
â¡ Polarity of CAM.LCLK is selectable via the POLCLK bit in the CTRLCLOCK register. Although data is latched on rising CAM.LCLK in the timing
diagrams, these timing parameters also apply to falling CAM.LCLK when POLCLK = 1.
C3
CAM.LCLK
CAM.VS
C1
C3
C7
CAM.HS
CAM.D[7:0]
C8
C7
C8
C6 C5
C5
C6
U1 Y1 V1 Yn
Figure 5--26. Camera Interface Timings
August 2002 -- Revised August 2004
SPRS197D 151
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