OMAP5910JGDY2 Datasheet, PDF (16/171 Pages) Texas Instruments – Dual-Core Processor

Introduction
2 Introduction
This section describes the main features of the OMAP5910 device, lists the terminal assignments, and
describes the function of each terminal. This data manual also provides a detailed description section,
electrical specifications, parameter measurement information, and mechanical data about the available
packaging.
2.1 Description
The OMAP5910 is a highly integrated hardware and software platform, designed to meet the application
processing needs of next-generation embedded devices.
The OMAP™ platform enables OEMs and ODMs to quickly bring to market devices featuring rich user
interfaces, high processing performance, and long battery life through the maximum flexibility of a fully
integrated mixed processor solution.
The dual-core architecture provides benefits of both DSP and RISC technologies, incorporating a
TMS320C55x DSP core and a high-performance TI925T ARM core.
The OMAP5910 device is designed to run leading open and embedded RISC-based operating systems, as
well as the Texas Instruments (TI) DSP/BIOS™ software kernel foundation, and is available in a 289-ball
MicroStar BGA™ package.
The OMAP5910 is targeted at the following applications:
• Applications processing devices
• Mobile communications
-- 802.11
-- Bluetooth™ wireless technology
-- GSM (including GPRS and EDGE)
-- CDMA
-- Proprietary government and other
• Video and image processing (MPEG4, JPEG, Windows® Media Video, etc.)
• Advanced speech applications (text-to-speech, speech recognition)
• Audio processing (MPEG-1 Audio Layer3 [MP3], AMR, WMA, AAC, and other GSM speech codecs)
• Graphics and video acceleration
• Generalized web access
• Data processing (fax, encryption/decryption, authentication, signature verification and watermarking)
2.1.1 TMS320C55x DSP Core
The DSP core of the OMAP5910 device is based on the TMS320C55x DSP generation CPU processor core.
The C55x DSP architecture achieves high performance and low power through increased parallelism and total
focus on reduction in power dissipation. The CPU supports an internal bus structure composed of one program
bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA
activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle.
In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.
OMAP, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments.
Bluetooth is a trademark owned by Bluetooth SIG, Inc.
Windows is a registered trademark of Microsoft Corporation.
Other trademarks are the property of their respective owners.
16 SPRS197D
August 2002 -- Revised August 2004