BQ24297 Datasheet, PDF (35/48 Pages) Texas Instruments – I2C Controlled 3A Single Cell USB Charger

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SLUSBP6A – SEPTEMBER 2013 – REVISED OCTOBER 2013
Battery Short Protection
If the battery voltage falls below V_short (2V typical), the device immediately turns off BATFET to disable the
battery charging or supplement mode. 1ms later, the BATFET turns on and charge the battery with 100mA
current. The device does not turn on BATFET to discharge a battery that is below 2.5V.
System Over-Current Protection
If the system is shorted or exceeds the over-current limit, the device latches off BATFET. DC source insertion on
VBUS is required to reset the latch-off condition and turn on BATFET.
Serial Interface
The device uses I²C compatible interface for flexible charging parameter programming and instantaneous device
status reporting. I2C^TM is a bi-directional 2-wire serial interface developed by Philips Semiconductor (now NXP
Semiconductors). Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Devices
can be considered as masters or slaves when performing data transfers. A master is the device which initiates a
data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device
addressed is considered a slave.
The device operates as a slave device with address 6BH, receiving control inputs from the master device like
micro controller or a digital signal processor. The I²C interface supports both standard mode (up to 100kbits), and
fast mode (up to 400kbits).
Both SDA and SCL are bi-directional lines, connecting to the positive supply voltage via a current source or pull-
up resistor. When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain.
Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each
data bit transferred.
SDA
SCL
Data line stable;
Data valid
Change
of data
allowed
Figure 34. Bit Transfer on the I²C Bus
START and STOP Conditions
All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the
SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered busy after the START
condition, and free after the STOP condition.
Copyright © 2013, Texas Instruments Incorporated
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