BQ24297 Datasheet, PDF (20/48 Pages) Texas Instruments – I2C Controlled 3A Single Cell USB Charger

bq24296
bq24297
SLUSBP6A – SEPTEMBER 2013 – REVISED OCTOBER 2013
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Charge Termination/Timer Control Register REG05 (default 10011010, or 0x9A)
BIT
DESCRIPTION
NOTE
Charging Termination Enable
Bit 7 EN_TERM
0 – Disable, 1 – Enable
Default: Enable termination (1)
Bit 6 Reserved
0 - Reserved
I2C Watchdog Timer Setting
Bit 5
Bit 4
WATCHDOG[1] 00 – Disable timer, 01 – 40s, 10 – 80s, 11 – Default: 40s (01)
WATCHDOG[0] ^160s
Charging Safety Timer Enable
Bit 3 EN_TIMER
0 – Disable, 1 – Enable
Default: Enable (1)
Fast Charge Timer Setting
Bit 2
Bit 1
CHG_TIMER[1] 00 – 5 hrs, 01 – 8 hrs, 10 – 12 hrs, 11 – 20
CHG_TIMER[0] ^hrs
Default: 12 hrs (10)
(See Charging Safety Timer for details)
Bit 0 Reserved
0 - Reserved
Boost Voltage/Thermal Regulation Control Register REG06 (default 01110011, or 0x73)
BIT
DESCRIPTION
NOTE
Bit 7
Bit 6
Bit 5
BOOSTV[3]
BOOSTV[2]
BOOSTV[1]
512mV
256mV
128mV
Offset: 4.55V
Range: 4.55V – 5.51V
Default:4.998V(0111)
Bit 4 BOOSTV[0]
64mV
Bit 3
Bit 2
BHOT[1]
BHOT[0]
Set Boost Mode temperature monitor
threshold voltage to disable boost mode
Voltage to disable boost mode
00 – V_bhot1 (33% of REGN or 55◦C w/ 103AT
thermistor)
01 – V_bhot0 (36% of REGN or 60◦C w/ 103AT
thermistor)
10 – V_bhot2 (30% of REGN or 65◦C w/ 103AT
thermistor)
11 – Disable boost mode thermal protection.
Default: V_bhot1 (00)
Note: For BHOT[1:0]=11, boost mode operates without
temperature monitor and the NTC_FAULT is generated based
on V_bhot1 threshold
Thermal Regulation Threshold
Bit 1
Bit 0
TREG[1]
TREG[0]
00 – 60°C, 01 – 80°C, 10 – 100°C, 11 –
120°C
Default: 120°C (11)
Misc Operation Control Register REG07 (default 01001011, or 4B)
BIT
DESCRIPTION
Force DPDM detection
Bit 7
DPDM_EN
0 – Not in D+/D– detection;
1 – Force D+/D– detection when VBUS power is
presence
Safety Timer Setting during Input DPM and Thermal Regulation
Bit 6
TMR2X_EN
0 – Safety timer not slowed by 2X during input DPM
or thermal regulation,
1 – Safety timer slowed by 2X during input DPM or
thermal regulation
Force BATFET Off
Bit 5
BATFET_Disable
0 – Allow BATFET (Q4) turn on, 1 – Turn off
BATFET (Q4)
Bit 4
Reserved
0 - Reserved
Bit 3
Reserved
1 - Reserved
Bit 2
Reserved
0 - Reserved
Bit 1
INT_MASK[1]
0 – No INT during CHRG_FAULT, 1 – INT on
CHRG_FAULT
Bit 0
INT_MASK[0]
0 – No INT during BAT_FAULT, 1 – INT on
BAT_FAULT
NOTE
Default: Not in D+/D– detection (0), Back to 0
after detection complete
Default: Safety timer slowed by 2X (1)
Default: Allow BATFET (Q4) turn on(0)
Default: INT on CHRG_FAULT (1)
Default: INT on BAT_FAULT (1)
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