MSP430F2132-EP_16 Datasheet, PDF (34/72 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F2132-EP
SLAS913A – JULY 2013 – REVISED AUGUST 2013
www.ti.com
Crystal Oscillator LFXT1, Low-Frequency Mode⁽¹⁾⁽²⁾
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
f_LFXT1,LF
PARAMETER
LFXT1 oscillator crystal
frequency, LF mode 0, 1
TEST CONDITIONS
XTS = 0, LFXT1Sx = 0 or 1
V_CC
1.8 V to 3.6 V
MIN TYP MAX UNIT
32768
Hz
f_{LFXT1,LF,logic}
LFXT1 oscillator logic level
square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3
LF mode
1.8 V to 3.6 V 10000 32768 50000 Hz
OA_LF
Oscillation allowance for
LF crystals
XTS = 0, LFXT1Sx = 0,
f_LFXT1,LF = 32768 Hz, C_L,eff = 6 pF
XTS = 0, LFXT1Sx = 0,
f_LFXT1,LF = 32768 Hz, C_L,eff = 12 pF
XTS = 0, XCAPx = 0
500
kΩ
200
1
C_L,eff
Integrated effective load
capacitance, LF mode⁽³⁾
XTS = 0, XCAPx = 1
XTS = 0, XCAPx = 2
5.5
pF
8.5
XTS = 0, XCAPx = 3
11
f_Fault,LF
Duty cycle, LF mode
Oscillator fault frequency,
LF mode⁽⁴⁾
XTS = 0, Measured at ACLK,
f_LFXT1,LF = 32768 Hz
XTS = 0, XCAPx = 0,
LFXT1Sx = 3⁽⁵⁾
2.2 V, 3 V
2.2 V, 3 V
30
50
70 %
10
10000 Hz
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
(2) Use of the LFXT1 Crystal Oscillator at T_A > 105°C is not ensured. It is recommended that an external digital clock source or the internal
DCO is used to provide clocking.
(3) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the crystal that is used.
(4) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(5) Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
f_VLO
df_VLO/dT
df_VLO/dV_CC
PARAMETER
VLO frequency
VLO frequency temperature drift⁽¹⁾
VLO frequency supply voltage drift⁽²⁾
T_A
-40°C to 85°C
125°C
V_CC
2.2 V, 3 V
2.2 V, 3 V
1.8 V to 3.6 V
MIN TYP
4
12
0.5
4
(1) Calculated using the box method:
[MAX(-40...125°C) - MIN(-40...125°C)]/MIN(-40...125°C)/[125°C - (-40°C)]
(2) Calculated using the box method: [MAX(1.8...3.6 V) - MIN(1.8...3.6 V)]/MIN(1.8...3.6 V)/(3.6 V - 1.8 V)
MAX
20
23
UNIT
kHz
%/°C
%/V
34
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