LM4F111B2QR Datasheet, PDF (339/1113 Pages) Texas Instruments – Microcontroller

Stellaris^® LM4F111B2QR Microcontroller
Register 74: Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode
Clock Gating Control (DCGCUART), offset 0x818
The DCGCUART register provides software the capability to enable and disable the UART modules
in deep-sleep mode. When enabled, a module is provided a clock. When disabled, the clock is
disabled to save power. This register provides the same capability as the legacy Deep-Sleep Mode
Clock Gating Control Register n DCGCn registers specifically for the watchdog modules and has
the same bit polarity as the corresponding DCGCn bits.
Important: This register should be used to control the clocking for the UART modules. To support
legacy software, the DCGC1 register is available. A write to the DCGC1 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
DCGC1 register can be read back correctly with a read of the DCGC1 register. Software
must use this register to support modules that are not present in the legacy registers.
If software uses this register to write a legacy peripheral (such as UART0), the write
causes proper operation, but the value of that bit is not reflected in the DCGC1 register.
If software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
Universal Asynchronous Receiver/Transmitter Deep-Sleep Mode Clock Gating Control (DCGCUART)
Base 0x400F.E000
Offset 0x818
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
D7
D6
D5
D4
D3
D2
D1
D0
Type RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:8
7
Name
reserved
D7
Type
RO
R/W
Reset
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Module 7 Deep-Sleep Mode Clock Gating Control
Value Description
1 Enable and provide a clock to UART module 7 in deep-sleep
mode.
0 UART module 7 is disabled.
6
D6
R/W
0
UART Module 6 Deep-Sleep Mode Clock Gating Control
Value Description
1 Enable and provide a clock to UART module 6 in deep-sleep
mode.
0 UART module 6 is disabled.
April 25, 2012
339
Texas Instruments-Advance Information