LM4F111B2QR Datasheet, PDF (26/1113 Pages) Texas Instruments – Microcontroller

Table of Contents
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 724
Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 725
Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 726
Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 727
Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 728
Analog-to-Digital Converter (ADC) ............................................................................................. 729
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 750
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 751
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 753
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 755
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 758
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 760
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 765
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 766
Register 9: ADC Sample Phase Control (ADCSPC), offset 0x024 ...................................................... 768
Register 10: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 770
Register 11: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 772
Register 12: ADC Digital Comparator Interrupt Status and Clear (ADCDCISC), offset 0x034 ................. 773
Register 13: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 775
Register 14: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 777
Register 15: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 780
Register 16: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 780
Register 17: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 780
Register 18: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 780
Register 19: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 781
Register 20: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 781
Register 21: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 781
Register 22: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 781
Register 23: ADC Sample Sequence 0 Operation (ADCSSOP0), offset 0x050 ...................................... 783
Register 24: ADC Sample Sequence 0 Digital Comparator Select (ADCSSDC0), offset 0x054 .............. 785
Register 25: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 787
Register 26: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 787
Register 27: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 788
Register 28: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 788
Register 29: ADC Sample Sequence 1 Operation (ADCSSOP1), offset 0x070 ...................................... 790
Register 30: ADC Sample Sequence 2 Operation (ADCSSOP2), offset 0x090 ..................................... 790
Register 31: ADC Sample Sequence 1 Digital Comparator Select (ADCSSDC1), offset 0x074 .............. 791
Register 32: ADC Sample Sequence 2 Digital Comparator Select (ADCSSDC2), offset 0x094 .............. 791
Register 33: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 793
Register 34: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 794
Register 35: ADC Sample Sequence 3 Operation (ADCSSOP3), offset 0x0B0 ..................................... 795
Register 36: ADC Sample Sequence 3 Digital Comparator Select (ADCSSDC3), offset 0x0B4 .............. 796
Register 37: ADC Digital Comparator Reset Initial Conditions (ADCDCRIC), offset 0xD00 ..................... 797
Register 38: ADC Digital Comparator Control 0 (ADCDCCTL0), offset 0xE00 ....................................... 802
Register 39: ADC Digital Comparator Control 1 (ADCDCCTL1), offset 0xE04 ....................................... 802
Register 40: ADC Digital Comparator Control 2 (ADCDCCTL2), offset 0xE08 ....................................... 802
Register 41: ADC Digital Comparator Control 3 (ADCDCCTL3), offset 0xE0C ...................................... 802
Register 42: ADC Digital Comparator Control 4 (ADCDCCTL4), offset 0xE10 ....................................... 802
26
April 25, 2012
Texas Instruments-Advance Information