SM320F28335-HT_14 Datasheet, PDF (33/182 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-HT
www.ti.com
NAME
GPIO86
-
XA14
GPIO87
-
XA15
XRD
NAME
TRST
TCK
TMS
TDI
TDO
EMU0
EMU1
V_DD3VFL
TEST1
TEST2
XCLKOUT
XCLKIN
SPRS682E – DECEMBER 2010 – REVISED JANUARY 2014
Table 2-5. Signal Descriptions (GB) (continued)
DESCRIPTION ⁽¹⁾
General-Purpose Input/Output 86 (I/O/Z)
-
External Interface Address Line 14 (O)
General-Purpose Input/Output 87 (I/O/Z)
-
External Interface Address Line 15 (O)
External Interface Read Enable
Table 2-6. Signal Descriptions (PTP)
PIN NO.
DESCRIPTION ⁽¹⁾
JTAG
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the
operations of the device. If this signal is not connected or driven low, the device operates in its functional
mode, and the test reset signals are ignored.
78
NOTE: TRST is an active high test pin and must be maintained low at all times during normal device
operation. An external pulldown resistor is required on this pin. The value of this resistor should be based
on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers
adequate protection. Since this is application-specific, it is recommended that each target board be
validated for proper operation of the debugger and the application. (I, ↓)
87 JTAG test clock with internal pullup (I, ↑)
79
JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP
controller on the rising edge of TCK. (I, ↑)
76
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data)
on a rising edge of TCK. (I, ↑)
77
JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are
shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)
Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator system
and is defined as input/output through the JTAG scan. This pin is also used to put the device into
boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a
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rising edge on the TRST pin would latch the device into boundary-scan mode. (I/O/Z, 8 mA drive ↑)
NOTE: An external pullup resistor is required on this pin. The value of this resistor should be based on the
drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally
adequate. Since this is application-specific, it is recommended that each target board be validated for
proper operation of the debugger and the application.
Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator system
and is defined as input/output through the JTAG scan. This pin is also used to put the device into
boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a logic-low state, a
86
rising edge on the TRST pin would latch the device into boundary-scan mode. (I/O/Z, 8 mA drive ↑)
NOTE: An external pullup resistor is required on this pin. The value of this resistor should be based on the
drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ resistor is generally
adequate. Since this is application-specific, it is recommended that each target board be validated for
proper operation of the debugger and the application.
FLASH
84 3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.
81 Test Pin. Reserved for TI. Must be left unconnected. (I/O)
82 Test Pin. Reserved for TI. Must be left unconnected. (I/O)
CLOCK
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency,
or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 18:16 (XTIMCLK) and bit 2
138 (CLKMODE) in the XINTCNF2 register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can
be turned off by setting XINTCNF2[CLKOFF] to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed
in high-impedance state during a reset. (O/Z, 8 mA drive).
External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case, the X1
105 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.9-V oscillator is used to feed
clock to X1 pin), this pin must be tied to GND. (I)
(1) I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown
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