SM320F28335-HT_14 Datasheet, PDF (167/182 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-HT
www.ti.com
CLKX
FSX (int)
FSX (ext)
DX
(XDATDLY=00b)
DX
(XDATDLY=01b)
DX
(XDATDLY=10b)
SPRS682E – DECEMBER 2010 – REVISED JANUARY 2014
M1, M11
M2, M12
M13
M3, M12
M5
M5
M19
M20
M10
Bit 0
M9
Bit (n−1)
(n−2)
Bit 0
M6
Bit 0
M8
Bit (n−1)
M8
Figure 6-39. McBSP Transmit Timing
M7
(n−3)
M7
(n−2)
M7
Bit (n−1)
6.16.2 McBSP as SPI Master or Slave Timing
Table 6-56. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)⁽¹⁾
NO.
M30
M31
M32
M33
t_su(DRV-CKXL)
t_h(CKXL-DRV)
t_{su(BFXL-CKXH)}
t_c(CKX)
(1) Not production tested.
(2) 2P = 1/CLKG
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX high
Cycle time, CLKX
MASTER
MIN MAX
30
1
2P ⁽²⁾
SLAVE
MIN MAX
8P – 10
8P –10
8P + 10
16P
UNIT
ns
ns
ns
ns
Table 6-57. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)⁽¹⁾
NO.
PARAMETER
M24
M25
M28
t_h(CKXL-FXL)
t_d(FXL-CKXH)
t_{dis(FXH-DXHZ)}
M29
t_d(FXL-DXV)
(1) Not production tested.
(2) 2P = 1/CLKG
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
Disable time, DX high impedance following last data bit from
FSX high
Delay time, FSX low to DX valid
MASTER
MIN
2P ⁽²⁾
MAX
P
6
SLAVE
MIN MAX
6P + 6
UNIT
ns
ns
ns
6
4P + 6
ns
Copyright © 2010–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: SM320F28335-HT
Electrical Specifications 167