BQ25890_16 Datasheet, PDF (33/69 Pages) Texas Instruments – Adjustable Voltage USB On-the-Go Boost Mode

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bq25890, bq25892
SLUSC86B – MARCH 2015 – REVISED MAY 2016
9.2.14.2.2 Boost Mode Overvoltage Protection
When the VBUS voltage rises above regulation target and exceeds V_{OTG_OVP}, the device enters overvoltage
protection which stops switching, clears OTG_CONFIG bit and exits boost mode. During the overvoltage
duration, the fault register bit (BOOST_FAULT) is set high to indicate fault in boost operation. An INT is also
asserted to the host.
9.2.15 Battery Protection
9.2.15.1 Battery Overvoltage Protection (BATOVP)
The battery overvoltage limit is clamped at 4% above the battery regulation voltage. When battery over voltage
occurs, the charger device immediately disables charge. The fault register BAT_FAULT bit goes high and an INT
is asserted to the host.
9.2.15.2 Battery Over-Discharge Protection
When battery is discharged below V_{BAT_DPL}, the BAe batterTFET is turned off to protect battery from over
discharge. To recover from over-discharge, an input source is required at VBUS. When an input source is
plugged in, the BATFET turns on. Thy is charged with I_BATSHORT (typically 100 mA) current when the VBAT <
V_SHORT, or precharge current as set in IPRECHG register when the battery voltage is between V_SHORT and
V_BATLOWV.
9.2.15.3 System Overcurrent Protection
When the system is shorted or significantly overloaded (I_BAT > I_BATOP) so that its current exceeds the overcurrent
limit, the device latches off BATFET. Section BATFET Enable (Exit Shipping Mode) can reset the latch-off
condition and turn on BATFET
9.2.16 Serial Interface
The device uses I²C compatible interface for flexible charging parameter programming and instantaneous device
status reporting. I²C is a bi-directional 2-wire serial interface. Only two open-drain bus lines are required: a serial
data line (SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves when performing
data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals
to permit that transfer. At that time, any device addressed is considered a slave.
The device operates as a slave device with address 6BH, receiving control inputs from the master device like
micro controller or a digital signal processor through REG00-REG14. Register read beyond REG14 (0x14)
returns 0xFF. The I²C interface supports both standard mode (up to 100 kbits), and fast mode (up to 400 kbits).
When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain and must be connected to the
positive supply voltage via a current source or pull-up resistor.
9.2.16.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each
data bit transferred.
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