VCE6467T Datasheet, PDF (321/352 Pages) Texas Instruments – VCE6467T, AVCE6467T Digital Media System-on-Chip

VCE6467T, AVCE6467T
www.ti.com
SPRS690 – MARCH 2011
Table 6-121. Additional Input Timing Requirements of 4-Pin Chip-Select Option in Slave Mode⁽¹⁾
NO.
25
t_su(CSL-CLK)
26
t_d(CLK-CSH) ⁽²⁾
Setup time, SPI_CS[n] asserted at slave to first SPI_CLK edge
(rising or falling) at slave
Delay time, final falling edge SPI_CLK to SPI_CS[n] deasserted,
polarity = 0, phase = 0
Delay time, final falling edge SPI_CLK to SPI_CS[n] deasserted,
polarity = 0, phase = 1
Delay time, final rising edge SPI_CLK to SPI_CS[n] deasserted,
polarity = 1, phase = 0
Delay time, final rising edge SPI_CLK to SPI_CS[n] deasserted,
polarity = 1, phase = 1
-1G
MIN
2P + 6
0.5T + P + 6
P+6
0.5T + P + 6
P+6
UNIT
MAX
ns
ns
(1) T = period of SPI_CLK; P = period of SPI core clock
(2) Figure 6-87 shows only polarity = 0, phase = 0 as an example.
Table 6-122. Additional Output Switching Characteristics of 5-Pin Option in Slave Mode⁽¹⁾
NO.
SPI33 t_en(CSL-SOMI)
SPI34
SPI29
t_{dis(CSH-SOMI)}
t_en(CSL-EN)
SPI30 t_dis(CLK-ENZ) ⁽²⁾
37
t_dis(CSH-ENH) ⁽²⁾
PARAMETER
Enable time, master asserting SPI_CS[n] to slave driving
SPI_SOMI valid
Disable time, master deasserting SPI_CS[n] to slave driving
SPI_SOMI high impedance
Enable time, master asserting SPI_CS[n] to slave driving SPI_EN
Disable time, final clock receive falling edge of SPI_CLK to slave
drive SPI_EN high impedance, polarity = 0, phase = 0,
SPIINT0.ENABLE HIGHZ = 1
Disable time, final clock receive rising edge of SPI_CLK to slave
drive SPI_EN high impedance, polarity = 0, phase = 1,
SPIINT0.ENABLE HIGHZ = 1
Disable time, final clock receive rising edge of SPI_CLK to slave
drive SPI_EN high impedance, polarity = 1, phase = 0,
SPIINT0.ENABLE HIGHZ = 1
Disable time, final clock receive falling edge of SPI_CLK to slave
drive SPI_EN high impedance, polarity = 1, phase = 1,
SPIINT0.ENABLE HIGHZ = 1
Disable time, SPI_CS[n] deassertion to slave drive SPI_EN high
impedance, polarity = 0, phase = 0,
SPIINT0.ENABLE HIGHZ = 1
Disable time, SPI_CS[n] deassertion to slave drive SPI_EN high
impedance, polarity = 0, phase = 1,
SPIINT0.ENABLE HIGHZ = 1
Disable time, SPI_CS[n] deassertion to slave drive SPI_EN high
impedance, polarity = 1, phase = 0,
SPIINT0.ENABLE HIGHZ = 1
Disable time, SPI_CS[n] deassertion to slave drive SPI_EN high
impedance, polarity = 1, phase = 1,
SPIINT0.ENABLE HIGHZ = 1
-1G
MIN
MAX
UNIT
P + 6 ns
P + 6 ns
6 ns
1.5P + 6
1.5P + 6
ns
1.5P + 6
1.5P + 6
P+6
P+6
ns
P+6
P+6
(1) T = period of SPI_CLK; P = period of SPI core clock
(2) Figure 6-87 shows only polarity = 0, phase = 0 as an example.
Copyright © 2011, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 321
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