VCE6467T Datasheet, PDF (288/352 Pages) Texas Instruments – VCE6467T, AVCE6467T Digital Media System-on-Chip

VCE6467T, AVCE6467T
SPRS690 – MARCH 2011
www.ti.com
DMARQ
DMACK
STOP (DIOW) ^(A)
HDMARDY (DIOR) ^(A)
t_ACK
t_ACK
DSTROBE (IORDY) ^(A)
DD[15:0]
t_UI
t_ENV
t_ENV
t_ZIORDY
t_AZ
t_FS
t_ZAD
t_ZFS
t_FS
t_ZAD
t_DZFS
t_DVS
t_DVH
DA[2:0],
ATA_CS0,
ATA_CS1
t_ACK
A. The definitions for the DIOW:STOP, DIOR:HDMARDY, and IORDY:DSTROBE signal lines are not in effect until
DMARQ and DMACK are asserted.
Figure 6-66. ATA Initiating an Ultra DMA Data-In Burst Timing
t_2CYC
DSTROBE
(IORDY)
DD[15:0]
t_CYC(A)
t_DH
t_DS
t_CYC(A)
t_DS
t_DH
t_DH
A. While DSTROBE (IORDY) timing is t_CYC at the device, it may be different at the host due to propagation delay
differences on the cable.
Figure 6-67. ATA Sustained Ultra DMA Data-In Data Transfer Timing
288 Peripheral Information and Electrical Specifications
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