ADC08DL502 Datasheet, PDF (32/43 Pages) Texas Instruments – Low Power, 8-Bit, Dual 500 MSPS A/D Converter

1.4.1 Note Regarding Clock Phase Adjust
This is a feature intended to help the system designer remove
small imbalances in clock distribution traces at the board level
when multiple ADCs are used. Please note, however, that
enabling this feature will reduce the dynamic performance
(ENOB, SNR, SFDR) some finite amount. The amount of
degradation increases with the amount of adjustment applied.
The user is strongly advised to (a) use the minimal amount of
adjustment; and (b) verify the net benefit of this feature in his
system before relying on it.
1.4.2 Note Regarding Extended Mode Offset Correction
When using the I or Q channel Offset Adjust registers, the
following information should be noted.
For offset values of +0000 0000 and −0000 0000, the actual
offset is not the same. By changing only the sign bit in this
case, an offset step in the digital output code of about 1/10th
of an LSB is experienced. This is shown more clearly in the
Figure below.
30174130
FIGURE 11. Extended Mode Offset Behavior
1.5 MULTIPLE ADC SYNCHRONIZATION
The ADC08DL502 has the capability to precisely reset its
sampling clock input to DCLK output relationship as deter-
mined by the user-supplied DCLK_RST pulse. This allows
multiple ADCs in a system to have their DCLK (and data) out-
puts transition at the same time with respect to the shared
CLK input that all the ADCs use for sampling.
The DCLK_RST signal must observe some timing require-
ments that are shown in Figure 7, Figure 8 and Figure 9 of the
Timing Diagrams. The DCLK_RST pulse must be of a mini-
mum width and its deassertion edge must observe setup and
hold times with respect to the CLK input rising edge. The du-
ration of the DCLK_RST pulse affects the length of time that
the digital output will take before providing valid data again
after the end of the reset condition. Therefore, the DCLK_RST
pulse width should be made reasonably short within the sys-
tem application constraints. These timing specifications are
listed as t_RH, t_RS, and t_PWR in the Converter Electrical Char-
acteristics.
The DCLK_RST signal can be asserted asynchronous to the
input clock. If DCLK_RST is asserted, the DCLK output is held
in a designated state. The state in which DCLK is held during
the reset period is determined by the mode of operation (SDR/
DDR) and the setting of the Output Edge configuration pin or
bit. (Refer to Figure 7, Figure 8 and Figure 9 for the DCLK
reset state conditions). Therefore, depending upon when the
DCLK_RST signal is asserted, there may be a narrow pulse
on the DCLK line during this reset event. When the
DCLK_RST signal is de-asserted in synchronization with the
CLK rising edge, there are three or four CLK cycles of sys-
tematic delay and the next CLK falling edge synchronizes the
DCLK output with those of other ADC08DL502s in the sys-
tem. The DCLK output is enabled again after a constant delay
(relative to the input clock frequency) which is equal to the
CLK input to DCLK output delay (t_OD). The device always ex-
hibits this delay characteristic in normal operation. The user
has the option of using a single-ended DCLK_RST signal, but
a differential DCLK_RST is strongly recommended due to its
superior timing specifications.
As shown in Figure 7, Figure 8, and Figure 9 of the Timing
Diagrams, there is a delay from the deassertion of
DCLK_RST to the reappearance of DCLK, which is equal to
several cycles of CLK plus t_OD. Note that the deassertion of
DCLK_RST is not latched in until the next falling edge of CLK.
For 1:2 Demux DDR 0° Mode, there are four CLK cycles of
delay; for all other modes, there are three CLK cycles of delay.
If the device is not programmed to allow DCLK to run contin-
uously, DCLK will become inactive during a calibration cycle.
Therefore, it is strongly recommended that DCLK only be
used as a data capture clock and not as a system clock.
The DCLK_RST pin should NOT be brought high while the
calibration process is running (while CalRun is high). Doing
so could cause a digital glitch in the digital circuitry, resulting
in corruption and invalidation of the calibration.
1.6 ADC TEST PATTERN
To aid in system debug, the ADC08DL502 has the capability
of providing a test pattern at the four output ports completely
independent of the input signal. The ADC is disengaged and
a test pattern generator is connected to the outputs including
OR. Each port is given a unique 8-bit word, alternating be-
tween 1's and 0's as described in Table 16 and Table 17.
TABLE 16. Test Pattern by Output Port in
1:2 Demultiplex Mode
Time Qd Id
Q
I OR Comments
T0 01h 02h 03h 04h 0
T1 FEh FDh FCh FBh 1
Pattern
T2 01h 02h 03h 04h 0 Sequence
T3 FEh FDh FCh FBh 1
n
T4 01h 02h 03h 04h 0
T5 01h 02h 03h 04h 0
T6 FEh FDh FCh FBh 1
Pattern
T7 01h 02h 03h 04h 0 Sequence
T8 FEh FDh FCh FBh 1
n+1
T9 01h 02h 03h 04h 0
T10 01h 02h 03h 04h 0
Pattern
T11 ...
...
... ... ... ^{Sequence n}
+2
With the part programmed into the non-demultiplex mode, the
test pattern’s order will be as described in Table 17.
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