ADC08DL502 Datasheet, PDF (13/43 Pages) Texas Instruments – Low Power, 8-Bit, Dual 500 MSPS A/D Converter

TABLE 8. AC Electrical Characteristics
Symbol
Parameter
Sampling Clock (CLK)
f_{CLK (max)}
Maximum Sampling Clock
Frequency
f_{CLK (min)}
Minimum Sampling Clock
Frequency
Sampling Clock Duty Cycle
t_CL
Sampling Clock Low Time
t_CH
Sampling Clock High Time
DCLK_RST (Note 17)
t_SR
Setup Time DCLK_RST±
t_HR
Hold Time DCLK_RST±
t_PWR
Pulse Width DCLK_RST±
Conditions
200 MHz ≤ f_CLK ≤ 500 MHz
(Note 12)
(Note 11)
(Note 11)
(Note 12) Differential
DCLK_RST
(Note 12) Differential
DCLK_RST
(Note 11)
Typ
50
1000
1000
90
30
Data Clock (DCLK)
DCLK Duty Cycle
(Note 11)
50
t_LHT
Differential Low-to-High
10% to 90%
150
Transition Time
t_HLT
Differential High-to-Low
10% to 90%
150
Transition Time
t_OSK
DCLK-to-Data Output Skew 50% of DCLK transition to 50%
±50
of Data transition
t_SU
Data-to-DCLK Set-Up Time DDR Mode, 90° DCLK (Note
750
11)
t_H
DCLK-to-Data Hold Time
DDR Mode, 90° DCLK (Note
890
11)
Data Input-to-Output
t_AD
Sampling (Aperture) Delay Input CLK+ Fall to Acquisition
1.6
of Data
t_AJ
Aperture Jitter
0.4
t_OD
Input Clock-to Data Output 50% of Input Clock transition to
4.0
Delay (in addition to Pipeline 50% of Data transition
Delay)
t_LAT
Pipeline Delay (Latency) in 1:2 DI Outputs
Demux Mode
DId Outputs
(Note 11, Note 14)
DQ Outputs
DQd Outputs
Pipeline Delay (Latency) in
Non-Demux Mode
(Note 11, Note 14)
DI Outputs
DQ Outputs
t_ORR
Over Range Recovery Time Differential V_IN step from ±1.2V
1
to 0V to get accurate
conversion
t_WU
PD low to Rated Accuracy
(Note 11)
500
Conversion (Wake-Up Time)
13
Lim
Units
(Limits)
500
MHz
200
MHz
20
% (min)
80
% (max)
400
ps (min)
400
ps (min)
ps
ps
4
CLK±
Cycles
(min)
45
% (min)
55
% (max)
ps
ps
ps
ps
ps
ns
ps (rms)
ns
13
Sampling
14
Clock
13
Cycles
14
13
13
Sampling
Clock
Cycle
ns
www.ti.com