ADC08DL502 Datasheet, PDF (28/43 Pages) Texas Instruments – Low Power, 8-Bit, Dual 500 MSPS A/D Converter

The default state of the Extended Control Mode is set upon
power-on reset (internally performed by the device) and is
shown in Table 14.
TABLE 14. Extended Control Mode Operation (Pin 41 Logic Low or Pin 14 Floating)
Feature
SDR or DDR Clocking
DDR Clock Phase (Note 17)
LVDS Output Amplitude (Note 17)
Calibration Delay (Note 17)
Full-Scale Range (Note 18)
Input Offset Adjust (Note 18)
Test Pattern
Resistor Trim Disable
Selectable Output Demultiplexer
Second DCLK Output (Note 17)
Sampling Clock Phase Adjust (Note 19)
Extended Control Mode Default State
DDR Clocking
Data changes with DCLK edge (0° phase)
Higher value indicated in Electrical Table
Short Delay
700 mV nominal for both channels
No adjustment for either channel
Not present at output
Trim enabled, DCLK not continuously present at output
1:2 demultiplex
Not present, pins 89 and 90
function as OR+ and OR-
No adjustment for fine, intermediate or coarse
1.3 THE SERIAL INTERFACE
IMPORTANT NOTE: During the initial write using the se-
rial interface, all nine registers must be written with de-
sired or default values. Subsequent writes to single
registers are allowed.
The 3-pin serial interface is enabled only when the device is
in the Extended Control mode. The pins of this interface are
Serial Clock (SCLK), Serial Data (SDATA) and Serial Inter-
face Chip Select (SCS). Nine write only registers are acces-
sible through this serial interface.
SCS: This signal should be asserted low while accessing a
register through the serial interface. Setup and hold times with
respect to the SCLK must be observed.
SCLK: Serial data input is accepted at the rising edge of this
signal. There is no minimum frequency requirement for SCLK.
SDATA: Each register access requires a specific 32-bit pat-
tern at this input. This pattern consists of a header, register
address and register value. The data is shifted in MSB first.
Setup and hold times with respect to the SCLK must be ob-
served. See the Timing Diagram.
Each Register access consists of 32 bits, as shown in Figure
6 of the Timing Diagrams. The fixed header pattern is 0000
0000 0001 (eleven zeros followed by a 1). The loading se-
quence is such that a "0" is loaded first. These 12 bits form
the header. The next 4 bits are the address of the register that
is to be written to and the last 16 bits are the data written to
the addressed register. The addresses of the various regis-
ters are indicated in Table 15.
Refer to the Register Description (1.4 REGISTER DESCRIP-
TION) for information on the data to be written to the registers.
Subsequent register accesses may be performed immediate-
ly, starting with the 33rd SCLK. This means that the SCS input
does not have to be de-asserted and asserted again between
register addresses. It is possible, although not recommended,
to keep the SCS input permanently enabled (at a logic low)
when using extended control.
Control register contents are retained when the device is put
into power-down mode.
IMPORTANT NOTE: Do not write to the Serial Interface when
calibrating the ADC. Doing so will impair the performance of
the device until it is re-calibrated correctly. Programming the
serial registers will also reduce dynamic performance of the
ADC for the duration of the register access time.
TABLE 15. Register Addresses
4-Bit Address
Loading Sequence:
A3 loaded after Fixed Header pattern, A0 loaded last
A3 A2 A1 A0 Hex Register Addressed
0 0 0 0 0h
Calibration
0 0 0 1 1h
Configuration
0 0 1 0 2h
"I" Ch Offset
0 0 1 1 3h "I" Ch Full-Scale Voltage
Adjust
0 1 0 0 4h
Reserved
0 1 0 1 5h
Reserved
0 1 1 0 6h
Reserved
0 1 1 1 7h
Reserved
1 0 0 0 8h
Reserved
1 0 0 1 9h Extended Configuration
1 0 1 0 Ah
"Q" Ch Offset
1 0 1 1 Bh "Q" Ch Full-Scale Voltage
Adjust
1 1 0 0 Ch
Reserved
1 1 0 1 Dh
Reserved
1 1 1 0 Eh Sampling Clock Phase
Fine Adjust
1 1 1 1 Fh Sample Clock Phase
Intermediate and Coarse
Adjust
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