ADC08DL502 Datasheet, PDF (29/43 Pages) Texas Instruments – Low Power, 8-Bit, Dual 500 MSPS A/D Converter

1.4 REGISTER DESCRIPTION
NOT ALL OF THE PINS, BITS, AND FEATURES WHICH
ARE MENTIONED IN THIS SECTION ARE TESTED IN
PRODUCTION TEST. SEE (Note 16, Note 17, Note 18, Note
19) IN THE PIN DESCRIPTIONS, THE CONVERTER ELEC-
TRICAL CHARACTERISTICS, Table 13, Table 14, AND
THE REGISTER DESCRIPTION FOR A DETAILED EXPLA-
NATION OF WHAT IS TESTED. IF THE SYSTEM APPLI-
CATION REQUIRES ADDITIONAL FEATURES OF THE
PRODUCT TO BE TESTED, CONTACT YOUR NATIONAL
SALES REPRESENTATIVE.
Nine write-only registers provide several control and config-
uration options in the Extended Control Mode. These regis-
ters have no effect when the device is in the Normal Control
Mode. Each register description below also shows the Power-
On Reset (POR) state of each control bit.
Calibration Register
Addr: 0h (0000b)
Write only (0x7FFF)
D15 D14 D13 D12 D11 D10 D9 D8
CAL 1 1 1 1 1 1 1
D7 D6 D5 D4 D3 D2 D1 D0
11111111
Bit 15
Bits 14:0
CAL: Calibration Enable. When this bit is set
1b, an on-command calibration cycle is
initiated. This function is exactly the same as
issuing an on-command calibration using the
CAL pin. (Note 16)
POR State: 0b
Must be set to 1b
Configuration Register
Addr: 1h (0001b)
Write only (0xB2FF)
D15 D14 D13 D12 D11 D10 D9 D8
1 0 nSD DCS DCP nDE OV OED
D7 D6 D5 D4 D3 D2 D1 D0
11111111
Bit 15
Bit 14
Bit 13
Bit 12
Must be set to 1b
Must be set to 0b
nSD: Second DCLK Output Enable. When
this bit is 1b, the device only has one DCLK
output and one OR output. When this bit is
0b, the device has two identical DCLK
outputs and no OR output. (Note 16)
POR State: 1b
DCS: Duty Cycle Stabilizer. When this bit is
set to 1b, a duty cycle stabilization circuit is
applied to the clock input. When this bit is set
to 0b the stabilization circuit is disabled.
(Note 16)
POR State: 1b
Bit 11
Bit 10
Bit 9
Bit 8
Bits 7:0
DCP: DDR Clock Phase. This bit only has an
effect in the DDR mode. When this bit is set
to 0b, the DCLK edges are time-aligned with
the data bus edges ("0° Phase"). When this
bit is set to 1b, the DCLK edges are placed
in the middle of the data bit-cells ("90°
Phase"), using the one-half speed DCLK
shown in Figure 4 as the phase reference.
(Note 16)
POR State: 0b
nDE: DDR Enable. When this bit is set to 0b,
data bus clocking follows the DDR (Double
Data Rate) mode whereby a data word is
output with each rising and falling edge of
DCLK. When this bit is set to a 1b, data bus
clocking follows the SDR (single data rate)
mode whereby each data word is output with
either the rising or falling edge of DCLK , as
determined by the OutEdge bit.
POR State: 0b
OV: Output Voltage. This bit determines the
LVDS outputs' voltage amplitude and has the
same function as the OutV pin that is used in
the normal control mode. When this bit is set
to 1b, the standard output amplitude is used.
When this bit is set to 0b, the reduced output
amplitude is used. (Note 16)
POR State: 1b
OED: Output Edge and Demultiplex Control.
This bit has two functions. When the device
is in SDR mode, this bit selects the DCLK
edge with which the data words transition
and has the same effect as the OutEdge pin
in the Non-extended control mode. When this
bit is set to 1b, the data outputs change with
the rising edge of DCLK+. When this bit is set
to 0b, the data output changes with the falling
edge of DCLK+. When the device is in DDR
mode, this bit selects the non-demultiplexed
mode when set to 1b. When the bit set to 0b,
the device is programmed into the
Demultiplexed mode. If the device is in DDR
and Non-Demultiplexed Mode, then the
DCLK has a 0° phase relationship with the
data; it is not possible to select the 90° phase
relationship.
POR State: 0b
Must be set to 1b
IMPORTANT NOTE: It is recommended that this register
should only be written upon power-up initialization as writing
it may cause disturbance on the DCLK output as this signal's
basic configuration is changed.
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