TM4C129EKCPDT Datasheet, PDF (312/2012 Pages) Texas Instruments – Tiva Microcontroller

System Control
Register 28: LDO Deep-Sleep Power Calibration (LDODPCAL), offset 0x1C0
This register provides factory determined values that are recommended for the VLDO field in the
LDODPCTL register while in Deep-Sleep mode. The reset value of this register cannot be determined
until the product has been characterized.
LDO Deep-Sleep Power Calibration (LDODPCAL)
Base 0x400F.E000
Offset 0x1C0
Type RO, reset 0x0000.1212
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOPLL
30KHZ
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
Bit/Field
31:16
15:8
7:0
Name
reserved
NOPLL
30KHZ
Type
RO
RO
RO
Reset
0x0
0x12
0x12
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Deep-Sleep without PLL
The value in this field is the suggested value for the VLDO field in the
LDODPCTL register when not using the PLL. This value provides the
lowest recommended LDO output voltage for use with the system clock.
Deep-Sleep with IOSC
The value in this field is the suggested value for the VLDO field in the
LDODPCTL register when not using the PLL. This value provides the
lowest recommended LDO output voltage for use with the low-frequency
internal oscillator.
312
June 18, 2014
Texas Instruments-Production Data