TM4C129EKCPDT Datasheet, PDF (1730/2012 Pages) Texas Instruments – Tiva Microcontroller

Ethernet Controller
Bit/Field
3:2
1
0
Name
FANSEL
FRXDVDET
reserved
Type
RW
RW
RO
Reset
0
Description
Fast Auto-Negotiation Select Configuration
This bit is preconfigured at reset by the EMACPC register. For custom
configuration see “Custom Configuration” on page 1588.
Adjusting these bits reduces the time it takes to auto-negotiate between
two PHYs. In Fast AN mode, both PHYs should be configured to the
same configuration. These two bits define the duration for each state
of the auto-negotiation process according to the table above. The new
duration time must be enabled by setting bit 4 (FASTANEN) of this
register.
Note:
Using this mode in cases where both link partners are not
configured to the same fast auto-negotiation configuration
might produce scenarios with unexpected behavior.
Value Description
0x0 Break Link Timer: 80 ms
Link Fail Inhibit Timer: 50 ms
Auto-Negate Wait Timer: 35 ms
0x1 Break Link Timer: 120 ms
Link Fail Inhibit Timer:75 ms
Auto-Negate Wait Timer: 50 ms
0x2 Break Link Timer: 240 ms
Link Fail Inhibit Timer:150 ms
Auto-Negate Wait Timer: 100 ms
0x3 reserved
0
FAST RXDV Detection
Enabling this feature allows the PHY to pass data to the MII interface
earlier. This bit is set to disabled if using the EMACPC register bits to
program the PHY configuration.
Value Description
0 Disable fast RXDV detection. The PHY operates in normal mode
where an internally asserted RXDV signal is sent to the MII
interface after detection of /J/K/.
1 An internal RXDV signal is asserted high on receive packet due
to detection of /J/ symbol only. Fast RXDV detection allows the
PHY to pass data to the MII interface earlier.
If a consecutive /K/ does not appear, RXERR is generated.
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1730
Texas Instruments-Production Data
June 18, 2014